How to deal with String Interpolation for VHDL target #1532

knapheide · 2024-09-09T10:05:06Z

knapheide
Sep 9, 2024

I have assert statements with string interpolation sprinkled all through my codebase.
As far as i can tell, this means i cant generate VHDL output anymore.

E.g. this example

class Test extends Component {
  val i = in port Bool()
  assert(i, L"Expected true, got $i")
}

object Test extends App {
  SpinalConfig(targetDirectory = "rtl").generateVhdl(new Test)
}

will produce this not-very-helpful error message:

[Progress] at 0.189 : Elaborate components
[Progress] at 0.192 : Checks and transforms
[Progress] at 0.194 : Generate VHDL to rtl
Exception in thread "main" java.lang.IllegalArgumentException: requirement failed
	at scala.Predef$.require(Predef.scala:268)
	at spinal.core.internals.ComponentEmitterVhdl.emitLeafStatements(ComponentEmitterVhdl.scala:638)
	at spinal.core.internals.ComponentEmitterVhdl.emitRegsLogic$1(ComponentEmitterVhdl.scala:519)
	at spinal.core.internals.ComponentEmitterVhdl.$anonfun$emitSynchronous$1(ComponentEmitterVhdl.scala:523)
	at spinal.core.internals.ComponentEmitterVhdl.$anonfun$emitSynchronous$1$adapted(ComponentEmitterVhdl.scala:523)
	at spinal.core.internals.ComponentEmitterVhdl.emitClockedProcess(ComponentEmitterVhdl.scala:495)
	at spinal.core.internals.ComponentEmitterVhdl.emitSynchronous(ComponentEmitterVhdl.scala:527)
	at spinal.core.internals.ComponentEmitterVhdl.$anonfun$emitArchitecture$14(ComponentEmitterVhdl.scala:264)
	at spinal.core.internals.ComponentEmitterVhdl.$anonfun$emitArchitecture$14$adapted(ComponentEmitterVhdl.scala:264)
	at scala.collection.Iterator.foreach(Iterator.scala:943)
	at scala.collection.Iterator.foreach$(Iterator.scala:943)
	at scala.collection.AbstractIterator.foreach(Iterator.scala:1431)
	at spinal.core.internals.ComponentEmitterVhdl.emitArchitecture(ComponentEmitterVhdl.scala:264)
	at spinal.core.internals.ComponentEmitterVhdl.<init>(ComponentEmitterVhdl.scala:1550)
	at spinal.core.internals.PhaseVhdl.compile(PhaseVhdl.scala:159)
	at spinal.core.internals.PhaseVhdl.$anonfun$impl$3(PhaseVhdl.scala:122)
	at spinal.core.internals.PhaseVhdl.$anonfun$impl$3$adapted(PhaseVhdl.scala:120)
	at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
	at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
	at spinal.core.internals.PhaseVhdl.impl(PhaseVhdl.scala:120)
	at spinal.core.internals.PhaseContext.doPhase(Phase.scala:184)
	at spinal.core.internals.SpinalVhdlBoot$.$anonfun$singleShot$6(Phase.scala:2843)
	at spinal.core.internals.SpinalVhdlBoot$.$anonfun$singleShot$6$adapted(Phase.scala:2841)
	at scala.collection.mutable.ResizableArray.foreach(ResizableArray.scala:62)
	at scala.collection.mutable.ResizableArray.foreach$(ResizableArray.scala:55)
	at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:49)
	at spinal.core.internals.SpinalVhdlBoot$.$anonfun$singleShot$1(Phase.scala:2841)
	at spinal.core.ScopeProperty$.sandbox(ScopeProperty.scala:71)
	at spinal.core.internals.SpinalVhdlBoot$.singleShot(Phase.scala:2776)
	at spinal.core.internals.SpinalVhdlBoot$.apply(Phase.scala:2771)
	at spinal.core.Spinal$.apply(Spinal.scala:420)
	at spinal.core.SpinalConfig.generateVhdl(Spinal.scala:186)
	at spinal.lib.Test$.delayedEndpoint$spinal$lib$Test$1(Test.scala:34)
	at spinal.lib.Test$delayedInit$body.apply(Test.scala:33)
	at scala.Function0.apply$mcV$sp(Function0.scala:39)
	at scala.Function0.apply$mcV$sp$(Function0.scala:39)
	at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:17)
	at scala.App.$anonfun$main$1$adapted(App.scala:80)
	at scala.collection.immutable.List.foreach(List.scala:431)
	at scala.App.main(App.scala:80)
	at scala.App.main$(App.scala:78)
	at spinal.lib.Test$.main(Test.scala:33)
	at spinal.lib.Test.main(Test.scala)

Is there an intended way to work around this?

For now i have defined this custom Phase, but im not sure im doing that right:

class PhaseVhdlAsserts extends PhaseNetlist {
  def impl(pc: PhaseContext): Unit = pc.walkStatements {
    case s: AssertStatement
        if !(s.message.isEmpty
          || (s.message.size == 1 && s.message.head.isInstanceOf[String])) =>
      val plainMessage = s.message.map {
        case str: String => str
        case obj         => s"[${obj.getClass().getSimpleName()}]"
      }.mkString
      s.insertNext {
        val cloned = s.copy(message = Seq(plainMessage))
        cloned.clockDomain = s.clockDomain
        cloned
      }
      s.removeStatement()
    case _ =>
  }
}

Dolu1990 · 2024-09-09T11:50:59Z

Dolu1990
Sep 9, 2024
Maintainer

Hi,

So, hardware asserts with string interpolation aren't supported by the VHDL backend.

The proper fix would be to add support for them in ComponentEmitterVhdl.scala:638

Would you feel like trying that + PR ^^?

For reference, here is how assert statements are emited in verilog :

SpinalHDL/core/src/main/scala/spinal/core/internals/ComponentEmitterVerilog.scala

Line 755 in 3524739

case assertStatement: AssertStatement => {

2 replies

knapheide Sep 9, 2024
Author

Ill try

Output should be VHDL 93 compatible, right?

Dolu1990 Sep 9, 2024
Maintainer

VHDL 93 compatible

Yes ^^

Thanks :)

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How to deal with String Interpolation for VHDL target #1532

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