case class BusReg extends Component {
  ...
  val reg1 = Reg(UInt(32 bits))
  val reg2 = Reg(UInt(32 bits))
  val rdat = Reg(UInt(32 bits))
  when(bus_wr && adr === 1) {reg1 := bus_wdat}
  when(bus_wr && adr === 2) {reg2 := bus_wdat}
  when(bus_rd)  {rdat := (addr===1) ? reg1 | reg2}
  ...
}
val bus = ClockDomain()
val wrk = ClockDomain()
val cksel = Bool()

val ckg = ClockSwitch(cksel , bus , wrk ) // ClockSwitch is what I make up
val areag = new ClockingArea(ckg) { 
  val cfg = BusReg()
}
val areaw = new ClockingArea(wrk){
  val c  = RegNext(areag.cfg.io.rdat * 2)
}