Discussions

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  Asynchronous Circuit Implementation

  mrberman87 asked Dec 11, 2024 in Q&A · Unanswered

  

  

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  PN code sequence generator and detector

  xueweiwujxw started Dec 10, 2024 in Ideas

  

  

  

  

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  Casting UFix to SFix

  hmohajeri asked Dec 5, 2024 in Q&A · Unanswered

  

  

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  How to get all generated signals including wire & reg from spinal

  facebreeze asked Nov 17, 2024 in Q&A · Closed · Answered

  

  

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  is there a state.next method for `SpinalEnum?

  goekce asked Nov 24, 2024 in Q&A · Answered

  

  

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  Is there a way to mix two bundle together ?

  facebreeze started Nov 28, 2024 in Ideas

  

  

  

  

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  Creating an alias to a case class

  goekce asked Nov 18, 2024 in Q&A · Closed · Answered

  

  

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  RegIf support for reading from/writing to Stream

  KireinaHoro asked Nov 5, 2024 in Q&A · Unanswered

  

  

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  Why always generate `timescale?

  yportne13 started Mar 29, 2024 in General

  

  

  

  

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  How to add comments to specific statements in verilog code, especially in when condition statements?

  Konecho asked Sep 14, 2024 in Q&A · Answered

  

  

  

  

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  Any superclass of Bundle that can handle inheritance errors ?

  soartang asked Sep 25, 2024 in Q&A · Unanswered

  

  

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  Add shift-left with saturation operator

  louiecaulfield started Oct 3, 2024 in Ideas

  

  

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  When two Modules have a common submodule, the naming of the generated hdl file will have a numeric suffix, is this by design?

  Konecho asked Sep 30, 2024 in Q&A · Unanswered

  

  

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  Is it possible to make ScoreboardInOrder more flexible

  calloftimereiver started Sep 17, 2024 in Ideas · Closed

  

  

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  how to limit data template to only BitVector?

  soartang asked Jul 21, 2024 in Q&A · Answered

  

  

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  How to deal with String Interpolation for VHDL target

  knapheide asked Sep 9, 2024 in Q&A · Unanswered

  

  

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  How to handle clock switch, clock gating?

  soartang started Sep 3, 2024 in General

  

  

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  use mill cross test before release.

  Readon started Sep 5, 2024 in Ideas

  

  

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  Verilog generation improve when doing *, +, shift with Integers

  soartang started Aug 13, 2024 in Ideas

  

  

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  Tilelink support / SoC negociation framework

  Dolu1990 started May 10, 2023 in Ideas

  

  

  

  

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  APB3Decoder

  ICJJ asked Jul 10, 2024 in Q&A · Unanswered

  

  

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  Something about module definition name

  yportne13 asked May 24, 2024 in Q&A · Unanswered

  

  

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  Next Release

  mrberman87 started May 23, 2024 in General · Closed

  

  

  

  

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  Rethink on pastValid function.

  Readon started Jun 3, 2024 in Ideas

  

  

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  Special Type for Addresses

  fayalalebrun started Jun 2, 2024 in Ideas

  

  

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