- Design a basic cpu structure (Lab4)
- Design cpu to implement R-Type instruction
- Design cpu to implement I-Type instruction
- Design cpu to implement S-Type instruction
- Design cpu to implement B-Type instruction
- Design cpu to implement U-Type instruction
- Design cpu to implement J-Type instruction
- Design cache for cpu
- Design bus for cpu
RISC-V has six types of instruction in total, they look like below:
opcode : Define the type of instruction
funct3 & funct7 : These two fields combined with opcode to determine what operation should be implemented
rs1 & rs2 : Adress of register
rd : Address of destination register
imm : Constant value in instructions
Here below are the instructions we need to implement for our cpu:
