Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's operands to the program counter.

A Fast, Low-Overhead On-chip Network

RISC-V CPU Core

AXI Adapter(s) for RISC-V Atomic Operations

AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

A 32-bit RISC-V Processor Designed with High-Level Synthesis

SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol

A RISC-V RV32 model ready for SMT program synthesis.

The HW-CBMC and EBMC Model Checkers for Verilog

A verification tool for many memory models

Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments

FuseSoC-based SoC for VeeR EH1 and EL2

Example designs using the Programming Design and Verification Language (PDVL)

Alloy models for automatic synthesis of memory model litmus test suites (from ASPLOS 2017)

Memory consistency modelling using Alloy

COATCheck

BaseJump STL: A Standard Template Library for SystemVerilog

SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions

ZSWatch - the Open Source Zephyr™ based Smartwatch, including both HW and FW.

Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generat…

advanced compilers

YosysHQ SVA AXI Properties

Learn FPGA Programming, published by Packt

Your Gateway to Embedded Software Development Excellence 👽