Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

cpu/{gd32v,stm32}/periph/adc: make ADC clock setable #19630

Merged
merged 3 commits into from
May 11, 2024
Merged

cpu/{gd32v,stm32}/periph/adc: make ADC clock setable #19630

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
4218fca
cpu/{gd32v,stm32}/periph/adc: make ADC clock setable
Enoch247 May 19, 2023
410e55d
cpu/{gd32v,stm32}/periph/adc: ensure max ADC speed is honored
Enoch247 May 11, 2024
4ed36bf
boards/nucleo-f767zi: increase ADC clock speed
Enoch247 May 19, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions boards/nucleo-f767zi/include/periph_conf.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -208,6 +208,7 @@ static const adc_conf_t adc_config[] = {
};

#define VBAT_ADC ADC_LINE(6) /**< VBAT ADC line */
#define ADC_CLK_MAX MHZ(36) /**< Use a faster than default ADC clock */
#define ADC_NUMOF ARRAY_SIZE(adc_config)
/** @} */

Expand Down
8 changes: 6 additions & 2 deletions cpu/gd32v/periph/adc.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@
* @}
*/

#include "compiler_hints.h"
#include "cpu.h"
#include "macros/units.h"
#include "mutex.h"
Expand All @@ -31,7 +32,9 @@
/**
* @brief Maximum allowed ADC clock speed
*/
#define MAX_ADC_SPEED MHZ(14)
#ifndef ADC_CLK_MAX
#define ADC_CLK_MAX MHZ(14)
#endif

/**
* @brief Allocate locks for all three available ADC devices
Expand Down Expand Up @@ -122,10 +125,11 @@ int adc_init(adc_t line)
}
/* set clock prescaler to get the maximal possible ADC clock value */
for (clk_div = 2; clk_div < 8; clk_div += 2) {
if ((CLOCK_CORECLOCK / clk_div) <= MAX_ADC_SPEED) {
if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
break;
}
}
maribu marked this conversation as resolved.
Show resolved Hide resolved
assume((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX);
RCU->CFG0 &= ~(RCU_CFG0_ADCPSC_2_Msk);
RCU->CFG0 |= ((clk_div / 2) - 1) << RCU_CFG0_ADCPSC_2_Pos;

Expand Down
8 changes: 6 additions & 2 deletions cpu/stm32/periph/adc_f1.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@
* @}
*/

#include "compiler_hints.h"
#include "cpu.h"
#include "mutex.h"
#include "periph/adc.h"
Expand All @@ -28,7 +29,9 @@
/**
* @brief Maximum allowed ADC clock speed
*/
#define MAX_ADC_SPEED MHZ(14)
#ifndef ADC_CLK_MAX
#define ADC_CLK_MAX MHZ(14)
#endif

/**
* @brief Allocate locks for all three available ADC devices
Expand Down Expand Up @@ -93,10 +96,11 @@ int adc_init(adc_t line)
}
/* set clock prescaler to get the maximal possible ADC clock value */
for (clk_div = 2; clk_div < 8; clk_div += 2) {
if ((periph_apb_clk(APB2) / clk_div) <= MAX_ADC_SPEED) {
if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
break;
}
}
assume((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX);
RCC->CFGR &= ~(RCC_CFGR_ADCPRE);
RCC->CFGR |= ((clk_div / 2) - 1) << 14;

Expand Down
8 changes: 6 additions & 2 deletions cpu/stm32/periph/adc_f2.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@
* @}
*/

#include "compiler_hints.h"
#include "cpu.h"
#include "mutex.h"
#include "periph/adc.h"
Expand All @@ -29,7 +30,9 @@
/**
* @brief Maximum allowed ADC clock speed
*/
#define MAX_ADC_SPEED MHZ(12)
#ifndef ADC_CLK_MAX
#define ADC_CLK_MAX MHZ(12)
#endif

/**
* @brief Default VBAT undefined value
Expand Down Expand Up @@ -86,10 +89,11 @@ int adc_init(adc_t line)
}
/* set clock prescaler to get the maximal possible ADC clock value */
for (clk_div = 2; clk_div < 8; clk_div += 2) {
if ((periph_apb_clk(APB2) / clk_div) <= MAX_ADC_SPEED) {
if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
break;
}
}
assume((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX);
ADC->CCR = ((clk_div / 2) - 1) << 16;

/* enable the ADC module */
Expand Down
8 changes: 6 additions & 2 deletions cpu/stm32/periph/adc_f4_f7.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@
* @}
*/

#include "compiler_hints.h"
#include "cpu.h"
#include "irq.h"
#include "mutex.h"
Expand All @@ -29,7 +30,9 @@
/**
* @brief Maximum allowed ADC clock speed
*/
#define MAX_ADC_SPEED MHZ(12)
#ifndef ADC_CLK_MAX
#define ADC_CLK_MAX MHZ(12)
#endif

/**
* @brief Maximum sampling time for each channel (480 cycles)
Expand Down Expand Up @@ -95,10 +98,11 @@ int adc_init(adc_t line)
dev(line)->CR2 = ADC_CR2_ADON;
/* set clock prescaler to get the maximal possible ADC clock value */
for (clk_div = 2; clk_div < 8; clk_div += 2) {
if ((periph_apb_clk(APB2) / clk_div) <= MAX_ADC_SPEED) {
if ((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX) {
break;
}
}
assume((periph_apb_clk(APB2) / clk_div) <= ADC_CLK_MAX);
ADC->CCR = ((clk_div / 2) - 1) << 16;
/* set sampling time to the maximum */
unsigned irq_state = irq_disable();
Expand Down
Loading