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19170: boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board r=benpicco a=gschorcht ### Contribution description This PR add the support for the [Sipeed Longan Nano](https://longan.sipeed.com/en) board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from `boards/seeedstudio-gd32` to `boards/common/gd32v`. **[Update]** At first glance, the existing peripheral definition for `seeedstudio-gd32` seems to fit exactly for `sipeed-longan-nano`. But at second glance it becomes clear that `seeedstudio-gd32` which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards. This PR depends on PR #19166 and includes this PR for the moment. ### Testing procedure t.b.d. ### Issues/PRs references Depends on PR #19166 Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
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# Copyright (c) 2023 Gunar Schorcht | ||
# | ||
# This file is subject to the terms and conditions of the GNU Lesser | ||
# General Public License v2.1. See the file LICENSE in the top level | ||
# directory for more details. | ||
# | ||
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config BOARD_HAS_HXTAL | ||
bool | ||
help | ||
Indicates that the board is providing an HXTAL oscillator | ||
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config BOARD_HAS_LXTAL | ||
bool | ||
help | ||
Indicates that the board is providing an LXTAL oscillator | ||
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config CLOCK_HXTAL | ||
int | ||
default 8000000 |
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CPU = gd32v |
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# include this module into the build | ||
INCLUDES += -I$(RIOTBOARD)/common/gd32v/include | ||
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# configure the serial interface | ||
PORT_LINUX ?= /dev/ttyUSB0 | ||
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) | ||
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# configure the flasher | ||
PROGRAMMER ?= openocd | ||
OPENOCD_CONFIG ?= $(RIOTBOARD)/common/gd32v/dist/openocd.cfg | ||
OPENOCD_DEBUG_ADAPTER ?= ftdi | ||
OPENOCD_FTDI_ADAPTER ?= openocd-usb | ||
OPENOCD_TRANSPORT = jtag | ||
OPENOCD_RESET_USE_CONNECT_ASSERT_SRST = 1 |
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/* | ||
* Copyright (C) 2023 Gunar Schorcht | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
*/ | ||
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/** | ||
* @defgroup boards_common_gd32v GD32V Common Configuration | ||
* @ingroup boards_common | ||
* @brief Definitions and configurations that are common for | ||
* all GD32VF103 boards. | ||
* | ||
* All boards using a MCU from the GD32VF103 family share some parts of their | ||
* configuration. | ||
*/ |
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/* | ||
* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net> | ||
* 2023 Gunar Schorcht <gunar@schorcht.net> | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
*/ | ||
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/** | ||
* @ingroup boards_common_gd32v | ||
* @{ | ||
* | ||
* @file | ||
* @brief Default timer configuration for GD32VF103 boards | ||
* | ||
* @author Koen Zandberg <koen@bergzand.net> | ||
* @author Gunar Schorcht <gunar@schorcht.net> | ||
*/ | ||
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#ifndef CFG_TIMER_DEFAULT_H | ||
#define CFG_TIMER_DEFAULT_H | ||
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#include "periph_cpu.h" | ||
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#ifdef __cplusplus | ||
extern "C" { | ||
#endif | ||
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/** | ||
* @name Timer configuration | ||
* | ||
* All GD32VF103xx variants have at least one advanced timer TIMER0 and two | ||
* general timers TIMER1 and TIMER2. GD32VF10x8 and GD32VF10xB have two | ||
* additional general timers TIMER3 and TIMER4. | ||
* | ||
* @{ | ||
*/ | ||
static const timer_conf_t timer_config[] = { | ||
{ | ||
.dev = TIMER1, | ||
.max = 0x0000ffff, | ||
.rcu_mask = RCU_APB1EN_TIMER1EN_Msk, | ||
.bus = APB1, | ||
.irqn = TIMER1_IRQn | ||
}, | ||
{ | ||
.dev = TIMER2, | ||
.max = 0x0000ffff, | ||
.rcu_mask = RCU_APB1EN_TIMER2EN_Msk, | ||
.bus = APB1, | ||
.irqn = TIMER2_IRQn | ||
}, | ||
#if defined(CPU_MODEL_GD32VF103C8T6) || defined(CPU_MODEL_GD32VF103CBT6) || \ | ||
defined(CPU_MODEL_GD32VF103R8T6) || defined(CPU_MODEL_GD32VF103RBT6) || \ | ||
defined(CPU_MODEL_GD32VF103T8U6) || defined(CPU_MODEL_GD32VF103TBU6) || \ | ||
defined(CPU_MODEL_GD32VF103V8T6) || defined(CPU_MODEL_GD32VF103VBT6) | ||
{ | ||
.dev = TIMER3, | ||
.max = 0x0000ffff, | ||
.rcu_mask = RCU_APB1EN_TIMER3EN_Msk, | ||
.bus = APB1, | ||
.irqn = TIMER3_IRQn | ||
}, | ||
{ | ||
.dev = TIMER4, | ||
.max = 0x0000ffff, | ||
.rcu_mask = RCU_APB1EN_TIMER4EN_Msk, | ||
.bus = APB1, | ||
.irqn = TIMER4_IRQn | ||
} | ||
#endif | ||
}; | ||
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#define TIMER_0_IRQN TIMER1_IRQn | ||
#define TIMER_1_IRQN TIMER2_IRQn | ||
#define TIMER_2_IRQN TIMER3_IRQn | ||
#define TIMER_3_IRQN TIMER4_IRQn | ||
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#define TIMER_NUMOF ARRAY_SIZE(timer_config) | ||
/** @} */ | ||
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#ifdef __cplusplus | ||
} | ||
#endif | ||
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#endif /* CFG_TIMER_DEFAULT_H */ | ||
/** @} */ |
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/* | ||
* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net> | ||
* 2023 Gunar Schorcht <gunar@schorcht.net> | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
*/ | ||
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/** | ||
* @ingroup boards_common_gd32v | ||
* @{ | ||
* | ||
* @file | ||
* @brief Default UART configuration for GD32VF103 boards | ||
* | ||
* @author Koen Zandberg <koen@bergzand.net> | ||
* @author Gunar Schorcht <gunar@schorcht.net> | ||
*/ | ||
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#ifndef CFG_UART_DEFAULT_H | ||
#define CFG_UART_DEFAULT_H | ||
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#include "periph_cpu.h" | ||
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#ifdef __cplusplus | ||
extern "C" { | ||
#endif | ||
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/** | ||
* @name UART configuration | ||
* @{ | ||
*/ | ||
static const uart_conf_t uart_config[] = { | ||
{ | ||
.dev = USART0, | ||
.rcu_mask = RCU_APB2EN_USART0EN_Msk, | ||
.rx_pin = GPIO_PIN(PORT_A, 10), | ||
.tx_pin = GPIO_PIN(PORT_A, 9), | ||
.bus = APB2, | ||
.irqn = USART0_IRQn, | ||
}, | ||
}; | ||
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#define UART_0_IRQN USART0_IRQn | ||
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#define UART_NUMOF ARRAY_SIZE(uart_config) | ||
/** @} */ | ||
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#ifdef __cplusplus | ||
} | ||
#endif | ||
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#endif /* CFG_UART_DEFAULT_H */ | ||
/** @} */ |
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/* | ||
* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net> | ||
* 2023 Gunar Schorcht <gunar@schorcht.net> | ||
* | ||
* This file is subject to the terms and conditions of the GNU Lesser | ||
* General Public License v2.1. See the file LICENSE in the top level | ||
* directory for more details. | ||
*/ | ||
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/** | ||
* @ingroup boards_common_gd32v | ||
* @{ | ||
* | ||
* @file | ||
* @brief Common peripheral configuration for GD32VF103 boards | ||
* | ||
* @author Koen Zandberg <koen@bergzand.net> | ||
* @author Gunar Schorcht <gunar@schorcht.net> | ||
*/ | ||
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#ifndef PERIPH_COMMON_CONF_H | ||
#define PERIPH_COMMON_CONF_H | ||
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#include "macros/units.h" | ||
#include "periph_cpu.h" | ||
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#ifdef __cplusplus | ||
extern "C" { | ||
#endif | ||
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#define CLOCK_CORECLOCK MHZ(108) /**< CPU clock frequency in Hz */ | ||
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#define CLOCK_AHB CLOCK_CORECLOCK /**< Equal to the CPU clock */ | ||
#define CLOCK_APB1 CLOCK_AHB/2 /**< Half AHB clock */ | ||
#define CLOCK_APB2 CLOCK_AHB /**< Equal to the AHB clock */ | ||
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#ifdef __cplusplus | ||
} | ||
#endif | ||
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#endif /* PERIPH_COMMON_CONF_H */ | ||
/** @} */ |
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ifneq (,$(filter saul_default,$(USEMODULE))) | ||
USEMODULE += saul_gpio | ||
endif | ||
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include $(RIOTBOARD)/common/gd32v/Makefile.dep |
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CPU = gd32v | ||
CPU_MODEL = gd32vf103vbt6 | ||
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# Put defined MCU peripherals here (in alphabetical order) | ||
FEATURES_PROVIDED += periph_timer | ||
FEATURES_PROVIDED += periph_uart | ||
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include $(RIOTBOARD)/common/gd32v/Makefile.features |
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# configure the serial interface | ||
PORT_LINUX ?= /dev/ttyUSB0 | ||
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) | ||
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# configure the flasher | ||
PROGRAMMER ?= openocd | ||
OPENOCD_DEBUG_ADAPTER ?= ftdi | ||
OPENOCD_FTDI_ADAPTER ?= openocd-usb | ||
OPENOCD_TRANSPORT = jtag | ||
OPENOCD_RESET_USE_CONNECT_ASSERT_SRST = 1 | ||
include $(RIOTBOARD)/common/gd32v/Makefile.include |
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