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19777: cpu/avr8_common: Prepare for rework ISR r=benpicco a=nandojve

### Contribution description

This prepares for rework how ISR is handled for AVR-8 platform. It is not expected changes on the behavior but tests on other boards were welcome to avoid regressions.

#### Improvements
 * Split UART state from ISR states. Now it is necessary two variables and GPIORx registers are automatically selected when available.
 * UART states now supports up to 8 UARTs.
 * Added AVR8_ISR macro do clean-up and hide internals related to ISR processing. This allows changes on ISR without any other changes on drivers.

### Testing procedure

Tests were conducted using atmega328p-xplained-mini and atxmega-a1u-xpro and the zigduino board was only built. The example thread_duel was used to test regressions.

Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
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@bors @nandojve
bors[bot] and nandojve authored Jul 11, 2023
2 parents 37c6233 + 1e23730 commit 1b8ad7c
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Showing 18 changed files with 393 additions and 717 deletions.
12 changes: 4 additions & 8 deletions cpu/atmega_common/atmega_cpu.c
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Expand Up @@ -2,7 +2,7 @@
* Copyright (C) 2014 Freie Universität Berlin, Hinnerk van Bruinehsen
* 2017 RWTH Aachen, Josua Arndt
* 2018 Matthew Blue
* 2021 Gerson Fernando Budke
* 2021-2023 Gerson Fernando Budke
* 2023 Hugues Larrive
*
* This file is subject to the terms and conditions of the GNU Lesser
Expand Down Expand Up @@ -30,6 +30,7 @@

#include "board.h"
#include "cpu.h"
#include "irq_arch.h"
#include "panic.h"

#define ENABLE_DEBUG 0
Expand Down Expand Up @@ -85,7 +86,7 @@ void __attribute__((weak)) avr8_clk_init(void)
* EIFR – External Interrupt Flag Register
* PCIFR – Pin Change Interrupt Flag Register
*/
ISR(BADISR_vect)
ISR(BADISR_vect, ISR_NAKED)
{
avr8_reset_cause();

Expand All @@ -109,10 +110,5 @@ ISR(BADISR_vect)
}

#if defined(BAT_LOW_vect)
ISR(BAT_LOW_vect, ISR_BLOCK)
{
avr8_enter_isr();
DEBUG("BAT_LOW\n");
avr8_exit_isr();
}
AVR8_ISR(BAT_LOW_vect, DEBUG, "BAT_LOW\n");
#endif
70 changes: 16 additions & 54 deletions cpu/atmega_common/periph/gpio.c
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Expand Up @@ -2,6 +2,8 @@
* Copyright (C) 2015 HAW Hamburg
* 2016 INRIA
* 2023 Hugues Larrive
* 2023 Gerson Fernando Budke
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
Expand All @@ -23,6 +25,7 @@
* @author Torben Petersen <petersen@ibr.cs.tu-bs.de>
* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
* @author Hugues Larrive <hugues.larrive@pm.me>
* @author Gerson Fernando Budke <nandojve@gmail.com>
*
* @}
*/
Expand All @@ -32,6 +35,7 @@
#include <avr/interrupt.h>

#include "cpu.h"
#include "irq.h"
#include "board.h"
#include "periph/gpio.h"
#include "periph_conf.h"
Expand Down Expand Up @@ -368,16 +372,13 @@ void gpio_irq_disable(gpio_t pin)

static inline void irq_handler(uint8_t int_num)
{
avr8_enter_isr();
config[int_num].cb(config[int_num].arg);
avr8_exit_isr();
}

#ifdef ENABLE_PCINT
/* inline function that is used by the PCINT ISR */
static inline void pcint_handler(uint8_t bank, uint8_t enabled_pcints)
{
avr8_enter_isr();
/* Find right item */
uint8_t idx = 0;

Expand Down Expand Up @@ -406,89 +407,50 @@ static inline void pcint_handler(uint8_t bank, uint8_t enabled_pcints)
enabled_pcints = enabled_pcints >> 1;
idx++;
}

avr8_exit_isr();
}
#ifdef MODULE_ATMEGA_PCINT0
ISR(PCINT0_vect, ISR_BLOCK)
{
pcint_handler(PCINT0_IDX, PCMSK0);
}
AVR8_ISR(PCINT0_vect, pcint_handler, PCINT0_IDX, PCMSK0);
#endif /* MODULE_ATMEGA_PCINT0 */

#ifdef MODULE_ATMEGA_PCINT1
ISR(PCINT1_vect, ISR_BLOCK)
{
pcint_handler(PCINT1_IDX, PCMSK1);
}
AVR8_ISR(PCINT1_vect, pcint_handler, PCINT1_IDX, PCMSK1);
#endif /* MODULE_ATMEGA_PCINT1 */

#ifdef MODULE_ATMEGA_PCINT2
ISR(PCINT2_vect, ISR_BLOCK)
{
pcint_handler(PCINT2_IDX, PCMSK2);
}
AVR8_ISR(PCINT2_vect, pcint_handler, PCINT2_IDX, PCMSK2);
#endif /* MODULE_ATMEGA_PCINT2 */

#ifdef MODULE_ATMEGA_PCINT3
ISR(PCINT3_vect, ISR_BLOCK)
{
pcint_handler(PCINT3_IDX, PCMSK3);
}
AVR8_ISR(PCINT3_vect, pcint_handler, PCINT3_IDX, PCMSK3);
#endif /* MODULE_ATMEGA_PCINT3 */

#endif /* ENABLE_PCINT */

ISR(INT0_vect, ISR_BLOCK)
{
irq_handler(0); /**< predefined interrupt pin */
}

ISR(INT1_vect, ISR_BLOCK)
{
irq_handler(1); /**< predefined interrupt pin */
}
AVR8_ISR(INT0_vect, irq_handler, 0); /**< predefined interrupt pin */
AVR8_ISR(INT1_vect, irq_handler, 1); /**< predefined interrupt pin */

#if defined(INT2_vect)
ISR(INT2_vect, ISR_BLOCK)
{
irq_handler(2); /**< predefined interrupt pin */
}
AVR8_ISR(INT2_vect, irq_handler, 2); /**< predefined interrupt pin */
#endif

#if defined(INT3_vect)
ISR(INT3_vect, ISR_BLOCK)
{
irq_handler(3); /**< predefined interrupt pin */
}
AVR8_ISR(INT3_vect, irq_handler, 3); /**< predefined interrupt pin */
#endif

#if defined(INT4_vect)
ISR(INT4_vect, ISR_BLOCK)
{
irq_handler(4); /**< predefined interrupt pin */
}
AVR8_ISR(INT4_vect, irq_handler, 4); /**< predefined interrupt pin */
#endif

#if defined(INT5_vect)
ISR(INT5_vect, ISR_BLOCK)
{
irq_handler(5); /**< predefined interrupt pin */
}
AVR8_ISR(INT5_vect, irq_handler, 5); /**< predefined interrupt pin */
#endif

#if defined(INT6_vect)
ISR(INT6_vect, ISR_BLOCK)
{
irq_handler(6); /**< predefined interrupt pin */
}
AVR8_ISR(INT6_vect, irq_handler, 6); /**< predefined interrupt pin */
#endif

#if defined(INT7_vect)
ISR(INT7_vect, ISR_BLOCK)
{
irq_handler(7); /**< predefined interrupt pin */
}
AVR8_ISR(INT7_vect, irq_handler, 7); /**< predefined interrupt pin */
#endif

#endif /* MODULE_PERIPH_GPIO_IRQ */
44 changes: 10 additions & 34 deletions cpu/atmega_common/periph/gpio_ll_irq.c
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Expand Up @@ -2,6 +2,7 @@
* Copyright (C) 2015 HAW Hamburg
* 2016 INRIA
* 2022 Otto-von-Guericke-Universität Magdeburg
* 2023 Gerson Fernando Budke
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
Expand All @@ -22,6 +23,7 @@
* @author Robert Hartung <hartung@ibr.cs.tu-bs.de>
* @author Torben Petersen <petersen@ibr.cs.tu-bs.de>
* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
* @author Gerson Fernando Budke <nandojve@gmail.com>
*
* @}
*/
Expand Down Expand Up @@ -117,63 +119,37 @@ int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig,

static void isr_exti(uint8_t exti)
{
avr8_enter_isr();
isr_ctx[exti].cb(isr_ctx[exti].arg);
avr8_exit_isr();
}

#ifdef INT0_vect
ISR(INT0_vect, ISR_BLOCK)
{
isr_exti(0);
}
AVR8_ISR(INT0_vect, isr_exti, 0);
#endif

#ifdef INT1_vect
ISR(INT1_vect, ISR_BLOCK)
{
isr_exti(1);
}
AVR8_ISR(INT1_vect, isr_exti, 1);
#endif

#ifdef INT2_vect
ISR(INT2_vect, ISR_BLOCK)
{
isr_exti(2);
}
AVR8_ISR(INT2_vect, isr_exti, 2);
#endif

#ifdef INT3_vect
ISR(INT3_vect, ISR_BLOCK)
{
isr_exti(3);
}
AVR8_ISR(INT3_vect, isr_exti, 3);
#endif

#ifdef INT4_vect
ISR(INT4_vect, ISR_BLOCK)
{
isr_exti(4);
}
AVR8_ISR(INT4_vect, isr_exti, 4);
#endif

#ifdef INT5_vect
ISR(INT5_vect, ISR_BLOCK)
{
isr_exti(5);
}
AVR8_ISR(INT5_vect, isr_exti, 5);
#endif

#ifdef INT6_vect
ISR(INT6_vect, ISR_BLOCK)
{
isr_exti(6);
}
AVR8_ISR(INT6_vect, isr_exti, 6);
#endif

#ifdef INT7_vect
ISR(INT7_vect, ISR_BLOCK)
{
isr_exti(7);
}
AVR8_ISR(INT7_vect, isr_exti, 7);
#endif
10 changes: 5 additions & 5 deletions cpu/atmega_common/periph/rtc.c
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@@ -1,5 +1,6 @@
/*
* Copyright (C) 2020 Benjamin Valentin
* 2023 Gerson Fernando Budke
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
Expand All @@ -17,10 +18,12 @@
* time across reboots or deep sleep.
*
* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
* @author Gerson Fernando Budke <nandojve@gmail.com>
*
* @}
*/

#include "irq.h"
#include "periph/rtc.h"

/* In .noinit so we don't reset the counter on reboot */
Expand All @@ -31,20 +34,17 @@ static rtc_alarm_cb_t alarm_cb;
static void *alarm_cb_arg;

/* will be called every second */
ISR(TIMER2_OVF_vect)
static inline void tmr2_ovf_handler(void)
{
avr8_enter_isr();

if (++tm_now.tm_sec > 59) {
rtc_tm_normalize(&tm_now);
}

if (alarm_cb && rtc_tm_compare(&tm_now, &tm_alarm) == 0) {
alarm_cb(alarm_cb_arg);
}

avr8_exit_isr();
}
AVR8_ISR(TIMER2_OVF_vect, tmr2_ovf_handler);

void rtc_init(void)
{
Expand Down
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