Fix the tail handling in R-V V sad

Signed-off-by: Rémi Denis-Courmont <remi@remlab.net>
FFmpeg · Jan 25, 2025 · a0a89ef · a0a89ef
1 parent e20ee9f
commit a0a89ef
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Showing 2 changed files with 19 additions and 19 deletions.
diff --git a/libavcodec/riscv/h26x/asm.S b/libavcodec/riscv/h26x/asm.S
@@ -20,46 +20,46 @@
 
 #include "libavutil/riscv/asm.S"
 
-.macro vsetvlstatic w, vlen, en, mn1, mn2, mn3, mn4, mn5, mn6
+.macro vsetvlstatic w, vlen, en, mn1, mn2, mn3, mn4, mn5, mn6, vta=ta
         .if \w == 2 && \vlen == 128
-                vsetivli        zero, \w, \en, \mn1, ta, ma
+                vsetivli        zero, \w, \en, \mn1, \vta, ma
         .elseif \w <= 4 && \vlen == 128
-                vsetivli        zero, \w, \en, \mn2, ta, ma
+                vsetivli        zero, \w, \en, \mn2, \vta, ma
         .elseif \w <= 8 && \vlen == 128
-                vsetivli        zero, \w, \en, \mn3, ta, ma
+                vsetivli        zero, \w, \en, \mn3, \vta, ma
         .elseif \w <= 16 && \vlen == 128
-                vsetivli        zero, \w, \en, \mn4, ta, ma
+                vsetivli        zero, \w, \en, \mn4, \vta, ma
         .elseif \w <= 32 && \vlen == 128
                 li              t0, \w
-                vsetvli         zero, t0, \en, \mn5, ta, ma
+                vsetvli         zero, t0, \en, \mn5, \vta, ma
         .elseif \w <= 4 && \vlen == 256
-                vsetivli        zero, \w, \en, \mn1, ta, ma
+                vsetivli        zero, \w, \en, \mn1, \vta, ma
         .elseif \w <= 8 && \vlen == 256
-                vsetivli        zero, \w, \en, \mn2, ta, ma
+                vsetivli        zero, \w, \en, \mn2, \vta, ma
         .elseif \w <= 16 && \vlen == 256
-                vsetivli        zero, \w, \en, \mn3, ta, ma
+                vsetivli        zero, \w, \en, \mn3, \vta, ma
         .elseif \w <= 32 && \vlen == 256
                 li              t0, \w
-                vsetvli         zero, t0, \en, \mn4, ta, ma
+                vsetvli         zero, t0, \en, \mn4, \vta, ma
         .elseif \w <= 64 && \vlen == 256
                 li              t0, \w
-                vsetvli         zero, t0, \en, \mn5, ta, ma
+                vsetvli         zero, t0, \en, \mn5, \vta, ma
         .else
                 li              t0, \w
-                vsetvli         zero, t0, \en, \mn6, ta, ma
+                vsetvli         zero, t0, \en, \mn6, \vta, ma
         .endif
 .endm
 
-.macro vsetvlstatic8 w, vlen
-        vsetvlstatic \w, \vlen, e8, mf8, mf4, mf2, m1, m2, m4
+.macro vsetvlstatic8 w, vlen, vta
+        vsetvlstatic \w, \vlen, e8, mf8, mf4, mf2, m1, m2, m4, \vta
 .endm
 
-.macro vsetvlstatic16 w, vlen
-        vsetvlstatic \w, \vlen, e16, mf4, mf2, m1, m2, m4, m8
+.macro vsetvlstatic16 w, vlen, vta
+        vsetvlstatic \w, \vlen, e16, mf4, mf2, m1, m2, m4, m8, \vta
 .endm
 
-.macro vsetvlstatic32 w, vlen
-        vsetvlstatic \w, \vlen, e32, mf2, m1, m2, m4, m8, m8
+.macro vsetvlstatic32 w, vlen, vta
+        vsetvlstatic \w, \vlen, e32, mf2, m1, m2, m4, m8, m8, \vta
 .endm
 
 .macro POW2_JMP_TABLE id, vlen

diff --git a/libavcodec/riscv/vvc/sad_rvv.S b/libavcodec/riscv/vvc/sad_rvv.S
@@ -37,7 +37,7 @@ SADVSET\vlen\w:
         vsetvlstatic32    \w, \vlen
         vmv.v.i           v0, 0
         vmv.s.x           v24, zero
-        vsetvlstatic16    \w, \vlen
+        vsetvlstatic16    \w, \vlen, tu
 SAD\vlen\w:
         addi              a5, a5, -2
         vle16.v           v8, (a0)