# TCL File Generated by Component Editor 13.0sp1

# Sat Aug 01 00:04:26 CST 2015

# DO NOT MODIFY

#

# axi_interconnect "axi_interconnect" v1.0

# CZW 2015.08.01.00:04:25

#

#

#

# request TCL package from ACDS 13.1

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package require -exact qsys 13.1

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# module axi_interconnect

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set_module_property DESCRIPTION ""

set_module_property NAME axi_interconnect

set_module_property VERSION 1.0

set_module_property INTERNAL false

set_module_property OPAQUE_ADDRESS_MAP true

set_module_property GROUP "Qsys Interconnect/AXI Interface"

set_module_property AUTHOR CZW

set_module_property DISPLAY_NAME axi_interconnect

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true

set_module_property EDITABLE true

set_module_property ANALYZE_HDL AUTO

set_module_property REPORT_TO_TALKBACK false

set_module_property ALLOW_GREYBOX_GENERATION false

#

# file sets

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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""

set_fileset_property QUARTUS_SYNTH TOP_LEVEL axi_interconnect

set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false

add_fileset_file axi_interconnect.sv SYSTEM_VERILOG PATH axi/axi_interconnect.sv TOP_LEVEL_FILE

add_fileset_file axi_interface.sv SYSTEM_VERILOG_INCLUDE PATH axi/axi_interface.sv

add_fileset_file axi_read_arbiter.sv SYSTEM_VERILOG PATH axi/axi_read_arbiter.sv

add_fileset_file axi_router.sv SYSTEM_VERILOG PATH axi/axi_router.sv

add_fileset_file axi_write_arbiter.sv SYSTEM_VERILOG PATH axi/axi_write_arbiter.sv

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# parameters

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# display items

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# connection point clock

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add_interface clock clock end

set_interface_property clock clockRate 0

set_interface_property clock ENABLED true

set_interface_property clock EXPORT_OF ""

set_interface_property clock PORT_NAME_MAP ""

set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1

#

# connection point reset

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add_interface reset reset end

set_interface_property reset associatedClock clock

set_interface_property reset synchronousEdges DEASSERT

set_interface_property reset ENABLED true

set_interface_property reset EXPORT_OF ""

set_interface_property reset PORT_NAME_MAP ""

set_interface_property reset SVD_ADDRESS_GROUP ""

add_interface_port reset reset reset Input 1