Abstract
System-level description languages in electronic system level are domain-specific sequential simulation languages using the shared-everything model in discrete-event modeling and simulation terminology. They implement sequential process-interaction worldview to take advantage of event partitioning for ease of programming and modularity. Therefore, their reference simulators can only be executed on a single physical core. Fast and accurate simulation is highly desirable for efficient and effective system design due to the ever-increasing complexity of embedded and cyber physical systems. Parallel discrete-event simulation (PDES) is the main technique to solve this problem for large-scale system-level models. PDES works based on state space partitioning by using the so-called logical process worldview. This paper proposes parallel system modeling and simulation language (PSML), along with its formalized distributed parallel simulation kernel, that provides execution of hardware models in order to improve simulation speed significantly. It will be shown that the proposed framework results in linear, super-linear speedups ranging from 11 × to 32 × for large-scale, complex PSML models in comparison with the SystemC reference simulator on a 12-core host.
Similar content being viewed by others
References
Sinaei S, Fatemi O (2018) Multi-objective algorithms for the application mapping problem in heterogeneous multiprocessor embedded system design. J Supercomput 1–27. https://doi.org/10.1007/s11227-018-2442-2
Fujimoto RM (2000) Parallel and distributed simulation systems. Wiley, New York
Fujimoto RM (2016) Research challenges in parallel and distributed simulation. ACM Trans Model Comput Simul (TOMACS) 26(4):22
Sang J et al (2018) Experiences with implementing parallel discrete-event simulation on GPU. J Supercomput 1–18. https://doi.org/10.1007/s11227-018-2254-4
Jafer S, Liu Q, Wainer G (2013) Synchronization methods in parallel and distributed discrete-event simulation. Simul Model Pract Theory 30:54–73
Bagrodia RL (1998) Parallel languages for discrete-event simulation models. IEEE Comput Sci Eng 5(2):27–38
Barnes Jr PD et al (2013) Warp speed: executing time warp on 1,966,080 cores. In: Proceedings of the 1st ACM SIGSIM Conference on Principles of Advanced Discrete Simulation. ACM
Society IC (2008) IEEE Standard 1076-2008—IEEE Standard for VHDL Language Reference Manual. IEEE
Society IC (2005) IEEE Standard 1364-2005—IEEE Standard for Verilog Hardware Description Language. IEEE
Society IC (2011) IEEE Standard 1666-2011—IEEE Standard for SystemC Language Reference Manual. IEEE
Society IC (2012) ANSI/IEEE Standard 1800-2012—IEEE Standard for System Verilog–Unified Hardware Design, Specification, and Verification Language. IEEE
Dömer R, Gerstlauer A, Gajski D (2002) SpecC language reference manual. In: SpecC technology open consortium
Dahl O-J, Nygaard K (1966) SIMULA: an ALGOL-based simulation language. Commun ACM 9(9):671–678
Xia W, Yao Y, Mu X (2012) An extended event graph-based modelling method for parallel and distributed discrete-event simulation. Math Comput Model Dyn Syst 18(3):287–306
Barros FJ (2008) Modeling and simulation of parallel adaptive divide-and-conquer algorithms. J Supercomput 43(3):241–255
Zhu L et al (2005) Parallel logic simulation of million-gate VLSI circuits. In: Modeling, analysis, and simulation of computer and telecommunication systems, 2005. 13th IEEE international symposium on. IEEE
Meraji S, Zhang W, Tropper C (2010) On the scalability and dynamic load-balancing of optimistic gate level simulation. IEEE Trans Comput Aided Des Integr Circuits Syst 29(9):1368–1380
Zhu Y, Wang B, Deng Y (2011) Massively parallel logic simulation with GPUs. ACM Trans Des Autom Electron Syst (TODAES) 16(3):29
Meraji S, Tropper C (2012) Optimizing techniques for parallel digital logic simulation. IEEE Trans Parallel Distrib Syst 23(6):1135–1146
Bailey ML, Briner JV Jr, Chamberlain RD (1994) Parallel logic simulation of VLSI systems. ACM Comput Surv (CSUR) 26(3):255–294
Gonsiorowski E, Lapre JM, Carothers CD (2017) Automatic model generation for gate-level circuit PDES with reverse computation. ACM Trans Model Comput Simul (TOMACS) 27(2):12
Martin DE et al (2002) Analysis and simulation of mixed-technology VLSI systems. J Parallel Distrib Comput 62(3):468–493
Li L, Huang H, Tropper C (2003) DVS: an object-oriented framework for distributed verilog simulation. In: Parallel and distributed simulation, 2003 (PADS 2003). proceedings. Seventeenth workshop on. IEEE
Sato S, Kobayashi R, Kise K (2018) ArchHDL: a novel hardware RTL modeling and high-speed simulation environment. IEICE Trans Inf Syst 101(2):344–353
Chen W et al (2014) Out-of-order parallel discrete event simulation for transaction level models. IEEE Trans Comput Aided Des Integr Circuits Syst 33(12):1859–1872
Chen W, Han X, Dömer R (2012) Out-of-order parallel simulation for ESL design. In: Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium
Schumacher C et al (2010) parSC: synchronous parallel systemC simulation on multi-core host architectures. In: Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. ACM
Vinco S et al (2012) SAGA: SystemC acceleration on GPU architectures. In: Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE. IEEE
Reder S et al (2015) Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures. Microprocess Microsyst 39(8):1063–1075
Schmidt T, Cheng Z, Dömer R (2018) Port call path sensitive conflict analysis for instance-aware parallel SystemC simulation. In: Design, automation and test in Europe. Dresden, Germany
Ventroux N, Sassolas T (2016) A new parallel SystemC kernel leveraging manycore architectures. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016. IEEE
Weinstock JH et al (2016) Parallel SystemC simulation for ESL design. ACM Trans Embed Comput Syst (TECS) 16(1):27
Schmidt T, Liu G, Dömer R (2017) Exploiting thread and data level parallelism for ultimate parallel SystemC simulation. In: Proceedings of the 54th Annual Design Automation Conference 2017. ACM
Cheng Z, Schmidt T, Domer R (2018) SystemC coding guideline for faster out-of-order parallel discrete event simulation. In: Proceedings of forum on specification and design languages. Munich, Germany
Doemer R (2016) Seven obstacles in the way of standard-compliant parallel SystemC simulation. IEEE Embed Syst Lett 8(4):81–84
Schmidt T (2018) A compiler infrastructure for static and hybrid analysis of discrete event system models. Ph.D. Dissertation, University of California, Irvine
Liu G (2017) Optimizing many-threads-to-many-cores mapping in parallel electronic system level simulation. Ph.D. Dissertation, University of California, Irvine
Dömer R, Liu G, Schmidt T (2017) Parallel simulation. In: Handbook of hardware/software codesign. Springer, Berlin, pp 533–564
Becker D, Moy M, Cornet J (2015) Challenges for the parallelization of loosely timed SystemC programs. In: IEEE international symposium on rapid system prototyping
Cox DR (2005) Ritsim: distributed systemC simulation. Department of Computer Engineering. Rochester Institute of Technology
Chopard B, Combes P, Zory J (2006) A conservative approach to systemC parallelization. In: Computational science—ICCS 2006. Springer, Berlin, pp 653–660
Mubarak M et al (2017) Enabling parallel simulation of large-scale HPC network systems. IEEE Trans Parallel Distrib Syst 28(1):87–100
Low Y-H et al (1999) Survey of languages and runtime libraries for parallel discrete-event simulation. Simulation 72(3):170–186
Perumalla K, Fujimoto R, Ogielski A (1998) TED—a language for modeling telecommunication networks. ACM SIGMETRICS Perform Eval Rev 25(4):4–11
Arora R, Bangalore P, Mernik M (2012) Raising the level of abstraction for developing message passing applications. J Supercomput 59(2):1079–1100
Thoman P et al (2018) A taxonomy of task-based parallel programming technologies for high-performance computing. J Supercomput 74(4):1422–1434
Poshtkohi A, Ghaznavi-Ghoushchi MB, Saghafi K (2017) The Parvicursor infrastructure to facilitate the design of Grid and Cloud computing systems. Computing 99(10):979–1006
Lamport L (1978) Time, clocks, and the ordering of events in a distributed system. Commun ACM 21(7):558–565
Liu G et al (2017) RISC compiler and simulator, Release V0.4.0: out-of-order parallel simulatable SystemC subset
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Poshtkohi, A., Ghaznavi-Ghoushchi, M.B. & Saghafi, K. PSML: parallel system modeling and simulation language for electronic system level. J Supercomput 75, 2691–2724 (2019). https://doi.org/10.1007/s11227-018-2682-1
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11227-018-2682-1