SchemaHD 4+

Name: SchemaHD
Author: Yasuaki Iwasaki

Generate Verilog & Simulation‪.‬

Yasuaki Iwasaki

Designed for iPad

- Free
- Offers In-App Purchases

iPad Screenshots

Description

FPGAs can dynamically generate logic circuits by means of configuration bit streams generated by languages such as Verilog and VHDL.
The generated logic circuit cannot be changed by communication data.
Therefore, it is very safe and cannot be attacked by hacking, which is a problem with CPUs, to execute arbitrary commands.
In addition, the generated logic circuits are all running simultaneously, so the highest performance parallel processing is being performed.
It can also generate logic circuits using configuration bitstreams at very high speed.
Most of the processing that can be done by the CPU can be done by the FPGA alone.
With advanced security and the highest performace, FPGAs are the perfect device for the modern age.
However, it takes a lot of effort to learn languages such as Verilog and VHDL.
There are other methods such as high-level synthesis from C/C++, but they require a lot of adjustments such as #pragma, and do not maximize the capabilities of the FPGA.
Schematics, not programming languages, are needed to maximize the capabilities of FPGAs and to further improve developer productivity.
Schematics allow you to grasp the whole picture at a glance, and can perfectly represent parallel processing.

SchemaHD is to draw a circuit diagram of a logic circuit, and it's possible to do generation of Verilog HDL and a simulation.
A made circuit diagram can be used by a different circuit diagram immediately.
You can also install wiring easily by touch operation.
A concept of interface is adopted as a terminal, so something structured of a AXI bus can also be used.
A terminal it's also possible to distinguish sound argument reason, negative logic and characteristic wiring of a clock and a reset by interface, and which is different in interface, they don't seem able to connect, it is.
You can input and output as a JSON file, so the made circuit diagram and interface are also capable of cooperation with other application.
Verilog HDL generated from a circuit diagram contains a comment of a terminal name and an instance name, so it's capable of the correspondence which is at the time of problem occurrence.
A network connection isn't needed, so it's also effective in information leak prevention.
A simple simulation is offered in the present, but it's expected to enhance it early.

18 Sept 2024

Version 1.2.4

Corrected a problem that causes the application to close abnormally when operating the tool selection in the upper right corner of the drawing edit screen.

The developer, Yasuaki Iwasaki, indicated that the app’s privacy practices may include handling of data as described below. For more information, see the developer’s privacy policy.

Data Not Collected

The developer does not collect any data from this app.

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Information

Provider

Yasuaki Iwasaki has identified itself as a trader for this app and confirmed that this product or service complies with European Union law.

Address: 522-0047 Shiga Hikone-shi 2770-12 Hinatsu-cyo Japan
Phone Number: +81 7028085624
Email: y_iwasaki@leto.eonet.ne.jp

Size

2.1 MB