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It was implemented incompletely. This commit implements it. As the result the assertion failure reported in #628 is fixed. To implement interface kind, signal kind is also defined. (signals are declared inside interface.) TODO: scope field for signal kind is not implemented yet. Signed-off-by: Masatake YAMATO <yamato@redhat.com>
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typedef interface c e; |
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iA input.vr /^interface iA {/;" I |
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clock input.vr /^ input clock CLOCK;$/;" s | ||
count input.vr /^ input [7:0] count PSAMPLE #-1 hdl_node "sample_if_verilog.counter";$/;" s | ||
cout input.vr /^ input [7:0] cout PSAMPLE #-1;$/;" s | ||
data input.vr /^ inout data PSAMPLE PHOLD NSAMPLE#-1 NHOLD #1;$/;" s | ||
data_in input.vr /^ input data_in PSAMPLE #-1 hdl_node "sample_if_verilog.data";$/;" s | ||
ddr_data_in input.vr /^ input ddr_data_in PSAMPLE NSAMPLE;$/;" s | ||
enable input.vr /^ output enable PHOLD#1;$/;" s | ||
nenable input.vr /^ output nenable PHOLD #1 hdl_node "sample_if_verilog.counter_en";$/;" s | ||
reset input.vr /^ output reset PHOLD#1;$/;" s | ||
sample_if input.vr /^interface sample_if {$/;" I |
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// Taken from: | ||
// http://www.asic-world.com/vera/hdl1.html#Interface_Declaration | ||
interface sample_if { | ||
// Other signals are sampled with respect to this | ||
input clock CLOCK; | ||
output reset PHOLD#1; | ||
output enable PHOLD#1; | ||
input [7:0] cout PSAMPLE #-1; | ||
inout data PSAMPLE PHOLD NSAMPLE#-1 NHOLD #1; | ||
input ddr_data_in PSAMPLE NSAMPLE; | ||
input data_in PSAMPLE #-1 hdl_node "sample_if_verilog.data"; | ||
input [7:0] count PSAMPLE #-1 hdl_node "sample_if_verilog.counter"; | ||
output nenable PHOLD #1 hdl_node "sample_if_verilog.counter_en"; | ||
} |
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