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drivers: pinctrl: nrf: add support for nordic,clock-enable
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Driver will be capable of retrieving such property from DT and apply it
accordingly.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
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@gmarull @carlescufi
gmarull authored and carlescufi committed Aug 6, 2024
1 parent b57481a commit 5e31886
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Showing 3 changed files with 16 additions and 34 deletions.
32 changes: 1 addition & 31 deletions drivers/pinctrl/pinctrl_nrf.c
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Original file line number Diff line number Diff line change
Expand Up @@ -101,9 +101,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uint32_t write = NO_WRITE;
nrf_gpio_pin_dir_t dir;
nrf_gpio_pin_input_t input;
#if NRF_GPIO_HAS_CLOCKPIN
bool clockpin = false;
#endif

if (drive_idx < ARRAY_SIZE(drive_modes)) {
drive = drive_modes[drive_idx];
Expand All @@ -122,9 +119,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
write = 1U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_UARTE_CLOCKPIN_TXD_NEEDED)
clockpin = true;
#endif
break;
case NRF_FUN_UART_RX:
NRF_PSEL_UART(reg, RXD) = psel;
Expand All @@ -136,9 +130,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
write = 1U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_UARTE_CLOCKPIN_RTS_NEEDED)
clockpin = true;
#endif
break;
case NRF_FUN_UART_CTS:
NRF_PSEL_UART(reg, CTS) = psel;
Expand All @@ -152,21 +143,12 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
write = 0U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_SPIM_CLOCKPIN_SCK_NEEDED)
clockpin = true;
#endif
break;
case NRF_FUN_SPIM_MOSI:
NRF_PSEL_SPIM(reg, MOSI) = psel;
write = 0U;
dir = NRF_GPIO_PIN_DIR_OUTPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_SPIM_CLOCKPIN_MOSI_NEEDED)
/* CLOCKPIN setting must not be applied to SPIM12x instances. */
if (!NRF_SPIM_IS_320MHZ_SPIM((void *)reg)) {
clockpin = true;
}
#endif
break;
case NRF_FUN_SPIM_MISO:
NRF_PSEL_SPIM(reg, MISO) = psel;
Expand All @@ -179,9 +161,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
NRF_PSEL_SPIS(reg, SCK) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_SPIS_CLOCKPIN_SCK_NEEDED)
clockpin = true;
#endif
break;
case NRF_FUN_SPIS_MOSI:
NRF_PSEL_SPIS(reg, MOSI) = psel;
Expand All @@ -192,9 +171,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
NRF_PSEL_SPIS(reg, MISO) = psel;
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_DISCONNECT;
#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_SPIS_CLOCKPIN_MISO_NEEDED)
clockpin = true;
#endif
break;
case NRF_FUN_SPIS_CSN:
NRF_PSEL_SPIS(reg, CSN) = psel;
Expand All @@ -216,9 +192,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
}
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_TWIM_CLOCKPIN_SCL_NEEDED)
clockpin = true;
#endif
break;
case NRF_FUN_TWIM_SDA:
NRF_PSEL_TWIM(reg, SDA) = psel;
Expand All @@ -227,9 +200,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
}
dir = NRF_GPIO_PIN_DIR_INPUT;
input = NRF_GPIO_PIN_INPUT_CONNECT;
#if NRF_GPIO_HAS_CLOCKPIN && defined(NRF_TWIM_CLOCKPIN_SDA_NEEDED)
clockpin = true;
#endif
break;
#endif /* defined(NRF_PSEL_TWIM) */
#if defined(NRF_PSEL_I2S)
Expand Down Expand Up @@ -395,7 +365,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
nrf_gpio_cfg(pin, dir, input, NRF_GET_PULL(pins[i]),
drive, NRF_GPIO_PIN_NOSENSE);
#if NRF_GPIO_HAS_CLOCKPIN
nrf_gpio_pin_clock_set(pin, clockpin);
nrf_gpio_pin_clock_set(pin, NRF_GET_CLOCK_ENABLE(pins[i]));
#endif
}
}
Expand Down
8 changes: 6 additions & 2 deletions include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h
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Original file line number Diff line number Diff line change
Expand Up @@ -24,9 +24,13 @@
*/

/** Position of the function field. */
#define NRF_FUN_POS 17U
#define NRF_FUN_POS 18U
/** Mask for the function field. */
#define NRF_FUN_MSK 0x7FFFU
#define NRF_FUN_MSK 0x3FFFU
/** Position of the clock enable field. */
#define NRF_CLOCK_ENABLE_POS 17U
/** Mask for the clock enable field. */
#define NRF_CLOCK_ENABLE_MSK 0x1U
/** Position of the invert field. */
#define NRF_INVERT_POS 16U
/** Mask for the invert field. */
Expand Down
10 changes: 9 additions & 1 deletion soc/nordic/common/pinctrl_soc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,8 @@ typedef uint32_t pinctrl_soc_pin_t;
((NRF_PULL_UP * DT_PROP(node_id, bias_pull_up)) << NRF_PULL_POS) | \
(DT_PROP(node_id, nordic_drive_mode) << NRF_DRIVE_POS) | \
((NRF_LP_ENABLE * DT_PROP(node_id, low_power_enable)) << NRF_LP_POS) |\
(DT_PROP(node_id, nordic_invert) << NRF_INVERT_POS) \
(DT_PROP(node_id, nordic_invert) << NRF_INVERT_POS) | \
(DT_PROP(node_id, nordic_clock_enable) << NRF_CLOCK_ENABLE_POS) \
),

/**
Expand All @@ -59,6 +60,13 @@ typedef uint32_t pinctrl_soc_pin_t;
*/
#define NRF_GET_FUN(pincfg) (((pincfg) >> NRF_FUN_POS) & NRF_FUN_MSK)

/**
* @brief Utility macro to obtain pin clock enable flag.
*
* @param pincfg Pin configuration bit field.
*/
#define NRF_GET_CLOCK_ENABLE(pincfg) (((pincfg) >> NRF_CLOCK_ENABLE_POS) & NRF_CLOCK_ENABLE_MSK)

/**
* @brief Utility macro to obtain pin inversion flag.
*
Expand Down

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