This script generates and analyzes prefix tree adders.

Performed a comparative study of Parallel Prefix Adders using Verilog HDL on Zynq-7000 APSoC (PL) from XIlinx. Circuits are simulated, synthesized and implemented using Vivado Design Suite.

code for printing verilog code of han carlson adder for n bits in python as well as java both.

Design challenge for the 50.002 module for the fastest 2-SAT solver and the best performance-area ratio for a 32-bit adder.