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gate-level

Here are 11 public repositories matching this topic...

RISC-V-CPU

jasonlin316 / RISC-V-CPU

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

processor vector verilog chip risc-v riscv32 gate-level place-and-route tape-out

Updated Dec 2, 2019
Verilog

A-Single-Path-Delay-32-Point-FFT-Processor

jasonlin316 / A-Single-Path-Delay-32-Point-FFT-Processor

A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.

pipeline dsp processor verilog fft butterfly radix-2 snr gate-level single-path-delay

Updated Jul 4, 2019
Verilog

gonsie / gates

Gate-level circuit model for ROSS

c simulation circuit ross discrete-events-simulations gate-level

Updated Feb 20, 2020
C

cad-polito-it / fenice

Customizable fault-simulation and gate-level editing library for sequential circuits

simulation cad event-driven gate-level

Updated Apr 20, 2021
C

alirezajaberirad / Object-Oriented-Modeling-of-Electronic-Circuits

This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022

image-processing object-oriented systemc object-oriented-programming gate-level system-modeling systemc-ams gate-level-simulation rtl-design

Updated Jul 29, 2022
C++

Archfx / TrojanWars

TrojanWars🐎 - Test Generation for activation of malicious hardware implants

security hardware rtl verilog trojans gate-level

Updated Jun 29, 2023
C

shawntsai0312 / NTUEE_ICDESIGN_23FALL_HW4

NTUEE IC Design 23Fall HW4

approximation verilog ntu logic-gates ic sigmoid ic-design gate-level ntuee

Updated Dec 12, 2023
Verilog

shawntsai0312 / NTUEE_ICDESIGN_23FALL_HW3

NTUEE IC Design 23Fall HW3

poker verilog ntu logic-gates ic ic-design gate-level ntuee

Updated Nov 20, 2023
Verilog

Aliiiw / Computer-Architecture-project

implement mips cpu in python

python postgresql gate-level

Updated Jul 12, 2022
Python

FarshidKeivanian / Optimization-of-JK-Flip-Flop-Layout-with-Minimal-Average-Power-of-Consumption-based-on-ACOR-Fuzzy-A

FuzzyACOR-Algorithm (Adaptive fuzzy metaheuristic based optimisation algorithm)

Updated May 10, 2022
MATLAB

gate_level

FPGA-Systems / gate_level

Реализация элементов цифровых схем из базовых логических элементов

fpga vhdl verilog gate-level basic-logic

Updated Feb 7, 2021
VHDL

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