From 75c66eaf2e052192255588f1694a2de5888afb62 Mon Sep 17 00:00:00 2001 From: Mike Beaton Date: Wed, 23 Oct 2024 23:04:39 +0100 Subject: [PATCH] GLOBAL: Align MDEPKG_NDEBUG dependent code with edk2 debug macro changes edk2 commit ae83c6b7fd83a5906e016a32027c1bcd792a624e updates the 'null' variants of the DebugLib macros (used when MDEPKG_NDEBUG is defined) so that they explicitly discard their parameters using `if (FALSE)` code blocks. These are understood as marking the contained code as referenced but unused by all supported compilers. This avoids the need for additional MDEPKG_NDEBUG dependent code in c files, to conditionally hide static methods or functions which are only used in debug macros. Now, such code can and must be removed. This commit updates the relevant MDEPKG_NDEBUG code in c files throughout edk2-platforms (there are only some 20 instances). We also fix a couple of cases where the wrapped variables had incorrectly not been marked STATIC. Since the RELEASE builds of all platforms which used this kind of code break after the above-mentioned edk2 commit, it is considered preferable to have one single cross-platform commit to edk2-platforms which resolves this, rarther than spreading the fix across multiple commits. Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Mike Beaton --- .../DisplayLink/DisplayLinkPkg/DisplayLinkGop/Gop.c | 3 +-- .../JunoPciHostBridgeLib/JunoPciHostBridgeLib.c | 3 --- .../ARM/Morello/Library/PlatformLib/PlatformLibMem.c | 2 -- .../ArmVExpressPciHostBridgeLib.c | 2 -- .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 3 --- Platform/RaspberryPi/Drivers/MmcDxe/MmcDebug.c | 12 +++++------- Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c | 3 --- .../P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c | 10 ---------- .../Pch/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c | 10 ---------- .../Pch/Library/PeiPchPolicyLib/PchPrintPolicy.c | 2 -- .../Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLib.c | 2 -- .../Pch/Library/PeiPchPolicyLib/PchPrintPolicy.c | 2 -- .../P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c | 10 ---------- Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.c | 2 -- .../Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.c | 2 -- .../NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c | 6 +----- Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/MmcDebug.c | 12 +++++------- 17 files changed, 12 insertions(+), 74 deletions(-) diff --git a/Drivers/DisplayLink/DisplayLinkPkg/DisplayLinkGop/Gop.c b/Drivers/DisplayLink/DisplayLinkPkg/DisplayLinkGop/Gop.c index 3e483afdba7..a8b2d79b260 100644 --- a/Drivers/DisplayLink/DisplayLinkPkg/DisplayLinkGop/Gop.c +++ b/Drivers/DisplayLink/DisplayLinkPkg/DisplayLinkGop/Gop.c @@ -349,7 +349,6 @@ DlGopSendScreenUpdate ( * @param videoMode * @return */ -#ifndef MDEPKG_NDEBUG STATIC inline UINT16 CalculateRefreshRate ( IN CONST struct VideoMode *VideoMode) @@ -367,7 +366,7 @@ CalculateRefreshRate ( } return Rate10Hz; } -#endif // MDEPKG_NDEBUG + /* ***************************************************************************************************** */ /* ***************************************************************************************************** */ /* ****************** START OF FUNCTIONS WHICH IMPLEMENT GOP INTERFACE ****************** */ diff --git a/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c b/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c index 83acf83c47d..eeafe23f1e0 100644 --- a/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c +++ b/Platform/ARM/JunoPkg/Library/JunoPciHostBridgeLib/JunoPciHostBridgeLib.c @@ -131,12 +131,9 @@ PciHostBridgeFreeRootBridges ( { } - -#ifndef MDEPKG_NDEBUG STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = { L"Mem", L"I/O", L"Bus" }; -#endif /** Inform the platform that the resource conflict happens. diff --git a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c index 54a870cfb3b..44e6772bb38 100644 --- a/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c +++ b/Platform/ARM/Morello/Library/PlatformLib/PlatformLibMem.c @@ -14,7 +14,6 @@ // The total number of descriptors, including the final "end-of-table" descriptor. #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 -#if !defined(MDEPKG_NDEBUG) STATIC CONST CHAR8 *gTblAttrDesc[] = { "UNCACHED_UNBUFFERED ", "NONSECURE_UNCACHED_UNBUFFERED", @@ -27,7 +26,6 @@ STATIC CONST CHAR8 *gTblAttrDesc[] = { "DEVICE ", "NONSECURE_DEVICE " }; -#endif #define LOG_MEM(desc) DEBUG (( \ DEBUG_ERROR, \ diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.c b/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.c index 4f6e0c5c44b..dd5c2257c84 100644 --- a/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.c +++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.c @@ -95,11 +95,9 @@ STATIC PCI_ROOT_BRIDGE mRootBridge = { (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath }; -#ifndef MDEPKG_NDEBUG STATIC CONST CHAR16 mAcpiAddrSpaceTypeStr[][4] = { L"Mem", L"I/O", L"Bus" }; -#endif /** Return all the root bridge instances in an array. diff --git a/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c index bdbc7cecc97..667dbe8456d 100644 --- a/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -234,12 +234,9 @@ PciHostBridgeFreeRootBridges ( } } - -#ifndef MDEPKG_NDEBUG STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = { L"Mem", L"I/O", L"Bus" }; -#endif /** Inform the platform that the resource conflict happens. diff --git a/Platform/RaspberryPi/Drivers/MmcDxe/MmcDebug.c b/Platform/RaspberryPi/Drivers/MmcDxe/MmcDebug.c index 22209fcaca1..43a440f5898 100644 --- a/Platform/RaspberryPi/Drivers/MmcDxe/MmcDebug.c +++ b/Platform/RaspberryPi/Drivers/MmcDxe/MmcDebug.c @@ -8,13 +8,11 @@ #include "Mmc.h" -#if !defined(MDEPKG_NDEBUG) -CONST CHAR8* mStrUnit[] = { "100kbit/s", "1Mbit/s", "10Mbit/s", "100MBit/s", - "Unknown", "Unknown", "Unknown", "Unknown" }; -CONST CHAR8* mStrValue[] = { "1.0", "1.2", "1.3", "1.5", "2.0", "2.5", - "3.0", "3.5", "4.0", "4.5", "5.0", "5.5", - "6.0", "7.0", "8.0" }; -#endif +STATIC CONST CHAR8* mStrUnit[] = { "100kbit/s", "1Mbit/s", "10Mbit/s", "100MBit/s", + "Unknown", "Unknown", "Unknown", "Unknown" }; +STATIC CONST CHAR8* mStrValue[] = { "1.0", "1.2", "1.3", "1.5", "2.0", "2.5", + "3.0", "3.5", "4.0", "4.5", "5.0", "5.5", + "6.0", "7.0", "8.0" }; VOID PrintCID ( diff --git a/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c b/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c index 688b4f43c04..437f6f37f5a 100644 --- a/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c +++ b/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c @@ -19,8 +19,6 @@ #include #include -#if !defined(MDEPKG_NDEBUG) - static const char *tblAttrDesc[] = { "UNCACHED_UNBUFFERED ", @@ -32,7 +30,6 @@ static const char *tblAttrDesc[] = "DEVICE ", "NONSECURE_DEVICE " }; -#endif #define LOG_MEM(desc) DEBUG ((DEBUG_ERROR, desc, VirtualMemoryTable[Index].PhysicalBase, \ ( VirtualMemoryTable[Index].PhysicalBase+VirtualMemoryTable[Index].Length - 1), \ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c index a5b18613bc7..fc63632b2b8 100644 --- a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c +++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c @@ -18,7 +18,6 @@ #include #include -#ifndef MDEPKG_NDEBUG /** Checks if the offset is valid for a given memory access width. Offset must align to width size. @@ -51,7 +50,6 @@ PchIsPcrOffsetValid ( } } } -#endif /** Read PCR register. @@ -69,9 +67,7 @@ PchPcrRead32 ( IN UINT32 Offset ) { -#ifndef MDEPKG_NDEBUG ASSERT (PchIsPcrOffsetValid (Offset, 4)); -#endif return MmioRead32 (PCH_PCR_ADDRESS (Pid, Offset)); } @@ -91,9 +87,7 @@ PchPcrRead16 ( IN UINT32 Offset ) { -#ifndef MDEPKG_NDEBUG ASSERT (PchIsPcrOffsetValid (Offset, 2)); -#endif return MmioRead16 (PCH_PCR_ADDRESS (Pid, Offset)); } @@ -134,9 +128,7 @@ PchPcrWrite32 ( IN UINT32 Data ) { -#ifndef MDEPKG_NDEBUG ASSERT (PchIsPcrOffsetValid (Offset, 4)); -#endif MmioWrite32 (PCH_PCR_ADDRESS (Pid, Offset), Data); return Data; @@ -161,9 +153,7 @@ PchPcrWrite16 ( IN UINT16 Data ) { -#ifndef MDEPKG_NDEBUG ASSERT (PchIsPcrOffsetValid (Offset, 2)); -#endif MmioWrite16 (PCH_PCR_ADDRESS (Pid, Offset), Data); return Data; diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c index 6f70733fe7e..f18625f828c 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c @@ -16,7 +16,6 @@ #include #include -#ifndef MDEPKG_NDEBUG /** Checks if the offset is valid for a given memory access width @@ -40,7 +39,6 @@ PchIsPcrOffsetValid ( return TRUE; } } -#endif /** Read PCR register. @@ -58,9 +56,7 @@ PchPcrRead32 ( IN UINT32 Offset ) { -#ifndef MDEPKG_NDEBUG ASSERT (PchIsPcrOffsetValid (Offset, 4)); -#endif return MmioRead32 (PCH_PCR_ADDRESS (Pid, Offset)); } @@ -80,9 +76,7 @@ PchPcrRead16 ( IN UINT32 Offset ) { -#ifndef MDEPKG_NDEBUG ASSERT (PchIsPcrOffsetValid (Offset, 2)); -#endif return MmioRead16 (PCH_PCR_ADDRESS (Pid, Offset)); } @@ -123,9 +117,7 @@ PchPcrWrite32 ( IN UINT32 Data ) { -#ifndef MDEPKG_NDEBUG ASSERT (PchIsPcrOffsetValid (Offset, 4)); -#endif MmioWrite32 (PCH_PCR_ADDRESS (Pid, Offset), Data); return Data; @@ -149,9 +141,7 @@ PchPcrWrite16 ( IN UINT16 Data ) { -#ifndef MDEPKG_NDEBUG ASSERT (PchIsPcrOffsetValid (Offset, 2)); -#endif MmioWrite16 (PCH_PCR_ADDRESS (Pid, Offset), Data); return Data; diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPrintPolicy.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPrintPolicy.c index a5a830f3dac..777735a6393 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPrintPolicy.c +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPrintPolicy.c @@ -454,9 +454,7 @@ PchPrintSerialIoConfig ( ) { UINTN Index; -#ifndef MDEPKG_NDEBUG static UINT8 DeviceName[PCH_MAX_SERIALIO_CONTROLLERS][5] = {"I2C0","I2C1","I2C2","I2C3","I2C4","I2C5","SPI0","SPI1","SPI2","UA00","UA01","UA02"}; -#endif DEBUG ((DEBUG_INFO, "------------------ PCH Serial IO Config ------------------\n")); DEBUG_CODE_BEGIN (); diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLib.c b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLib.c index a1c20ba04ff..2f3c77d043c 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoLib.c @@ -44,9 +44,7 @@ PchStepping ( UINT8 RevId; UINT16 LpcDeviceId; UINTN LpcBaseAddress; -#ifndef MDEPKG_NDEBUG static CHAR8 *UnsupportedPchMsg = "Unsupported PCH. Supported stepping starting from"; -#endif if (mPchStepping != PchSteppingMax) { return mPchStepping; diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPrintPolicy.c b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPrintPolicy.c index e540dc95b0e..5480302df1d 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPrintPolicy.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPrintPolicy.c @@ -434,9 +434,7 @@ PchPrintSerialIoConfig ( ) { UINTN Index; -#ifndef MDEPKG_NDEBUG static CHAR16 DeviceName[11][5] = {L"I2C0",L"I2C1",L"I2C2",L"I2C3",L"I2C4",L"I2C5",L"SPI0",L"SPI1",L"UA00",L"UA01",L"UA02"}; -#endif DEBUG ((DEBUG_INFO, "------------------ PCH Serial IO Config ------------------\n")); DEBUG_CODE_BEGIN (); diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c index c4f3740c86a..b7a0776898a 100644 --- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c @@ -16,7 +16,6 @@ #include #include -#ifndef MDEPKG_NDEBUG /** Checks if the offset is valid for a given memory access width. Offset must align to width size. @@ -49,7 +48,6 @@ PchIsPcrOffsetValid ( } } } -#endif /** Read PCR register. @@ -67,9 +65,7 @@ PchPcrRead32 ( IN UINT32 Offset ) { -#ifndef MDEPKG_NDEBUG ASSERT (PchIsPcrOffsetValid (Offset, 4)); -#endif return MmioRead32 (PCH_PCR_ADDRESS (Pid, Offset)); } @@ -89,9 +85,7 @@ PchPcrRead16 ( IN UINT32 Offset ) { -#ifndef MDEPKG_NDEBUG ASSERT (PchIsPcrOffsetValid (Offset, 2)); -#endif return MmioRead16 (PCH_PCR_ADDRESS (Pid, Offset)); } @@ -132,9 +126,7 @@ PchPcrWrite32 ( IN UINT32 Data ) { -#ifndef MDEPKG_NDEBUG ASSERT (PchIsPcrOffsetValid (Offset, 4)); -#endif MmioWrite32 (PCH_PCR_ADDRESS (Pid, Offset), Data); return Data; @@ -159,9 +151,7 @@ PchPcrWrite16 ( IN UINT16 Data ) { -#ifndef MDEPKG_NDEBUG ASSERT (PchIsPcrOffsetValid (Offset, 2)); -#endif MmioWrite16 (PCH_PCR_ADDRESS (Pid, Offset), Data); return Data; diff --git a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.c b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.c index 9e394a63ba7..ea9c1d3eb9b 100644 --- a/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.c +++ b/Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.c @@ -35,7 +35,6 @@ STATIC MV_GPIO_DEVICE_PATH mDevicePathTemplate = { } }; -#if !defined(MDEPKG_NDEBUG) /** Routine Description: @@ -79,7 +78,6 @@ MvGpioValidate ( return EFI_SUCCESS; } -#endif /** diff --git a/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.c b/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.c index 3d6b8978009..bef865b7c0e 100644 --- a/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.c +++ b/Silicon/Marvell/Drivers/Gpio/MvPca95xxDxe/MvPca95xxDxe.c @@ -53,7 +53,6 @@ STATIC PCA95XX_PIN_COUNT mPca95xxPinCount[PCA95XX_MAX_ID] = { PCA9557_PIN_COUNT, }; -#if !defined(MDEPKG_NDEBUG) /** Routine Description: @@ -101,7 +100,6 @@ MvPca95xxValidate ( return EFI_SUCCESS; } -#endif EFI_STATUS EFIAPI diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c index 7f11d7a6025..00842e1be9d 100644 --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -168,13 +168,9 @@ STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { } }; -#ifndef MDEPKG_NDEBUG -STATIC -GLOBAL_REMOVE_IF_UNREFERENCED -CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { +STATIC CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { L"Mem", L"I/O", L"Bus" }; -#endif #define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | \ EFI_PCI_HOST_BRIDGE_MEM64_DECODE diff --git a/Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/MmcDebug.c b/Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/MmcDebug.c index 21d9229e4c8..f4aea9eb4eb 100644 --- a/Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/MmcDebug.c +++ b/Silicon/Sophgo/SG2042Pkg/Drivers/MmcDxe/MmcDebug.c @@ -9,13 +9,11 @@ #include "Mmc.h" -#if !defined(MDEPKG_NDEBUG) -CONST CHAR8* mStrUnit[] = { "100kbit/s", "1Mbit/s", "10Mbit/s", "100MBit/s", - "Unknown", "Unknown", "Unknown", "Unknown" }; -CONST CHAR8* mStrValue[] = { "1.0", "1.2", "1.3", "1.5", "2.0", "2.5", - "3.0", "3.5", "4.0", "4.5", "5.0", "5.5", - "6.0", "7.0", "8.0" }; -#endif +STATIC CONST CHAR8* mStrUnit[] = { "100kbit/s", "1Mbit/s", "10Mbit/s", "100MBit/s", + "Unknown", "Unknown", "Unknown", "Unknown" }; +STATIC CONST CHAR8* mStrValue[] = { "1.0", "1.2", "1.3", "1.5", "2.0", "2.5", + "3.0", "3.5", "4.0", "4.5", "5.0", "5.5", + "6.0", "7.0", "8.0" }; /** Print the Card Identification (CID) register.