Improve GateMate support: pass Verilog defines and parameters and sea…

…rch for p_r tool in PATH
olofk · Apr 23, 2024 · 8143f90 · 8143f90
1 parent 6114cbf
commit 8143f90
Showing 1 changed file with 14 additions and 3 deletions.
diff --git a/edalize/gatemate.py b/edalize/gatemate.py
@@ -71,7 +71,7 @@ def configure_main(self):
                 else:
                     ccf_file = f.name
 
-        # Pass trellis tool options to yosys
+        # Pass GateMate tool options to yosys
         self.edam["tool_options"] = {
             "yosys": {
                 "arch": "gatemate",
@@ -84,16 +84,27 @@ def configure_main(self):
         }
 
         yosys = Yosys(self.edam, self.work_root)
-        yosys.configure()
+
+        # Always define CCGM
+        yosys.vlogdefine["CCGM"] = 1
+
+        for k, v in self.tool_options.get("vlogdefine", []):
+            yosys.vlogdefine[k] = v
+
+        for k, v in self.tool_options.get("vlogparam", []):
+            yosys.vlogparam[k] = v
+
+        yosys.configure_main()
 
         # Write Makefile
         commands = EdaCommands()
         commands.commands = yosys.commands
 
         # PnR & image generation
+        commands.add_var("P_R := $(shell which p_r)")
         targets = self.name + "_00.cfg.bit"
         command = [
-            "p_r",
+            "$(P_R)",
             "-A",
             device_number,
             "-i",