Skip to content

Commit

Permalink
Update ox-reveal, verilog-mode package forks
Browse files Browse the repository at this point in the history
  • Loading branch information
@kaushalmodi
kaushalmodi committed Aug 10, 2016
1 parent 6498d08 commit 7a6f15d
Show file tree
Hide file tree
Showing 2 changed files with 97 additions and 54 deletions.
2 changes: 1 addition & 1 deletion elisp/ox-reveal
Submodule ox-reveal updated 2 files
+4 −1 Readme.org
+25 −16 ox-reveal.el
149 changes: 96 additions & 53 deletions elisp/verilog-mode/verilog-mode.el
View file
Original file line number Diff line number Diff line change
Expand Up @@ -123,7 +123,7 @@
;;

;; This variable will always hold the version number of the mode
(defconst verilog-mode-version "2016-04-23-5f6855e-vpo"
(defconst verilog-mode-version "2016-07-24-cdd9115-vpo"
"Version of this Verilog mode.")
(defconst verilog-mode-release-emacs nil
"If non-nil, this version of Verilog mode was released with Emacs itself.")
Expand Down Expand Up @@ -1138,32 +1138,67 @@ be replaced, and will remain symbolic.
For example, imagine a submodule uses parameters to declare the size of its
inputs. This is then used by an upper module:

module InstModule (o,i);
parameter WIDTH;
input [WIDTH-1:0] i;
endmodule
module InstModule (o,i);
parameter WIDTH;
input [WIDTH-1:0] i;
parameter type OUT_t;
output OUT_t o;
endmodule

module ExampInst;
InstModule
#(.PARAM(10))
instName
(/*AUTOINST*/
.i (i[PARAM-1:0]));
module ExampInst;
/*AUTOOUTPUT*/
// Beginning of automatic outputs
output OUT_t o;
// End of automatics

InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
.i (i[WIDTH-1:0]),
.o (o));

Note even though WIDTH=10, the AUTOINST has left the parameter as
a symbolic name. Likewise the OUT_t is preserved as the name
from the instantiated module.

Note even though PARAM=10, the AUTOINST has left the parameter as a
symbolic name. If `verilog-auto-inst-param-value' is set, this will
If `verilog-auto-inst-param-value' is set, this will
instead expand to:

module ExampInst;
InstModule
#(.PARAM(10))
instName
(/*AUTOINST*/
.i (i[9:0]));"
/*AUTOOUTPUT*/
// Beginning of automatic outputs
output upper_t o;
// End of automatics

InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
.i (i[9:0]),
.o (o));

Note that the instantiation now has \"i[9:0]\" as the WIDTH
was expanded. Likewise the data type of \"o\" in the AUTOOUTPUT
is now upper_t, from the OUT_t parameter override.
This second expansion of parameter types can be overridden with
`verilog-auto-inst-param-value-type'."
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-inst-param-value 'safe-local-variable 'verilog-booleanp)

(defcustom verilog-auto-inst-param-value-type t
"Non-nil means expand parameter type in instantiations.
If nil, leave parameter types as symbolic names.

See `verilog-auto-inst-param-value'."
:version "25.1"
:group 'verilog-mode-auto
:type 'boolean)
(put 'verilog-auto-inst-param-value-type 'safe-local-variable 'verilog-booleanp)

(defcustom verilog-auto-inst-sort nil
"Non-nil means AUTOINST signals will be sorted, not in declaration order.
Also affects AUTOINSTPARAM. Declaration order is the default for
Expand Down Expand Up @@ -1768,7 +1803,7 @@ so there may be a large up front penalty for the first search."
(let (pt)
(while (and (not pt)
(re-search-forward regexp bound noerror))
(if (verilog-inside-comment-or-string-p)
(if (verilog-inside-comment-or-string-p (match-beginning 0))
(re-search-forward "[/\"\n]" nil t) ; Only way a comment or quote can end
(setq pt (match-end 0))))
pt))
Expand All @@ -1782,7 +1817,7 @@ so there may be a large up front penalty for the first search."
(let (pt)
(while (and (not pt)
(re-search-backward regexp bound noerror))
(if (verilog-inside-comment-or-string-p)
(if (verilog-inside-comment-or-string-p (match-beginning 0))
(re-search-backward "[/\"]" nil t) ; Only way a comment or quote can begin
(setq pt (match-beginning 0))))
pt))
Expand Down Expand Up @@ -2820,7 +2855,7 @@ find the errors."
))

(defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
(defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
(defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\|randcase\\)")
(defconst verilog-extended-complete-re
;; verilog-beg-of-statement also looks backward one token to extend this match
(concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\|\\<static\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
Expand Down Expand Up @@ -4576,7 +4611,7 @@ Limit search to point LIM."
(progn
(if
(verilog-re-search-backward
"\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
"\\<\\(randcase\\|case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
(progn
(cond
((match-end 1)
Expand Down Expand Up @@ -8633,12 +8668,20 @@ Return an array of [outputs inouts inputs wire reg assign const]."
(defvar create-lockfiles)
(defvar which-func-modes))

(defun verilog-read-sub-decls-sig (submoddecls comment port sig vec multidim mem)
(defun verilog-read-sub-decls-type (par-values portdata)
"For `verilog-read-sub-decls-line', decode a signal type."
(let* ((type (verilog-sig-type portdata))
(pvassoc (assoc type par-values)))
(cond ((member type '("wire" "reg")) nil)
(pvassoc (nth 1 pvassoc))
(t type))))

(defun verilog-read-sub-decls-sig (submoddecls par-values comment port sig vec multidim mem)
"For `verilog-read-sub-decls-line', add a signal."
;; sig eq t to indicate .name syntax
;;(message "vrsds: %s(%S)" port sig)
(let ((dotname (eq sig t))
portdata)
portdata)
(when sig
(setq port (verilog-symbol-detick-denumber port))
(setq sig (if dotname port (verilog-symbol-detick-denumber sig)))
Expand All @@ -8657,8 +8700,7 @@ Return an array of [outputs inouts inputs wire reg assign const]."
mem
nil
(verilog-sig-signed portdata)
(unless (member (verilog-sig-type portdata) '("wire" "reg"))
(verilog-sig-type portdata))
(verilog-read-sub-decls-type par-values portdata)
multidim nil)
sigs-inout)))
((or (setq portdata (assoc port (verilog-decls-get-outputs submoddecls)))
Expand All @@ -8676,8 +8718,7 @@ Return an array of [outputs inouts inputs wire reg assign const]."
;; Also for backwards compatibility we don't propagate
;; "input wire" upwards.
;; See also `verilog-signals-edit-wire-reg'.
(unless (member (verilog-sig-type portdata) '("wire" "reg"))
(verilog-sig-type portdata))
(verilog-read-sub-decls-type par-values portdata)
multidim nil)
sigs-out)))
((or (setq portdata (assoc port (verilog-decls-get-inputs submoddecls)))
Expand All @@ -8690,8 +8731,7 @@ Return an array of [outputs inouts inputs wire reg assign const]."
mem
nil
(verilog-sig-signed portdata)
(unless (member (verilog-sig-type portdata) '("wire" "reg"))
(verilog-sig-type portdata))
(verilog-read-sub-decls-type par-values portdata)
multidim nil)
sigs-in)))
((setq portdata (assoc port (verilog-decls-get-interfaces submoddecls)))
Expand All @@ -8703,7 +8743,7 @@ Return an array of [outputs inouts inputs wire reg assign const]."
mem
nil
(verilog-sig-signed portdata)
(verilog-sig-type portdata)
(verilog-read-sub-decls-type par-values portdata)
multidim nil)
sigs-intf)))
((setq portdata (and verilog-read-sub-decls-in-interfaced
Expand All @@ -8716,13 +8756,13 @@ Return an array of [outputs inouts inputs wire reg assign const]."
mem
nil
(verilog-sig-signed portdata)
(verilog-sig-type portdata)
(verilog-read-sub-decls-type par-values portdata)
multidim nil)
sigs-intf)))
;; (t -- warning pin isn't defined.) ; Leave for lint tool
)))))

(defun verilog-read-sub-decls-expr (submoddecls comment port expr)
(defun verilog-read-sub-decls-expr (submoddecls par-values comment port expr)
"For `verilog-read-sub-decls-line', parse a subexpression and add signals."
;;(message "vrsde: `%s'" expr)
;; Replace special /*[....]*/ comments inserted by verilog-auto-inst-port
Expand All @@ -8738,7 +8778,7 @@ Return an array of [outputs inouts inputs wire reg assign const]."
(let ((mlst (split-string (match-string 1 expr) "[{},]"))
mstr)
(while (setq mstr (pop mlst))
(verilog-read-sub-decls-expr submoddecls comment port mstr)))))
(verilog-read-sub-decls-expr submoddecls par-values comment port mstr)))))
(t
(let (sig vec multidim mem)
;; Remove leading reduction operators, etc
Expand Down Expand Up @@ -8768,9 +8808,9 @@ Return an array of [outputs inouts inputs wire reg assign const]."
;; If found signal, and nothing unrecognized, add the signal
;;(message "vrsde-rem: `%s'" expr)
(when (and sig (string-match "^\\s-*$" expr))
(verilog-read-sub-decls-sig submoddecls comment port sig vec multidim mem))))))
(verilog-read-sub-decls-sig submoddecls par-values comment port sig vec multidim mem))))))

(defun verilog-read-sub-decls-line (submoddecls comment)
(defun verilog-read-sub-decls-line (submoddecls par-values comment)
"For `verilog-read-sub-decls', read lines of port defs until none match.
Inserts the list of signals found, using submodi to look up each port."
(let (done port)
Expand All @@ -8788,13 +8828,13 @@ Inserts the list of signals found, using submodi to look up each port."
;; .name
((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*[,)/]")
(verilog-read-sub-decls-sig
submoddecls comment (match-string-no-properties 1) t ; sig==t for .name
submoddecls par-values comment (match-string-no-properties 1) t ; sig==t for .name
nil nil nil) ; vec multidim mem
(setq port nil))
;; .\escaped_name
((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*[,)/]")
(verilog-read-sub-decls-sig
submoddecls comment (concat (match-string-no-properties 1) " ") t ; sig==t for .name
submoddecls par-values comment (concat (match-string-no-properties 1) " ") t ; sig==t for .name
nil nil nil) ; vec multidim mem
(setq port nil))
;; random
Expand All @@ -8809,29 +8849,29 @@ Inserts the list of signals found, using submodi to look up each port."
(when port
(cond ((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
(verilog-read-sub-decls-sig
submoddecls comment port
submoddecls par-values comment port
(verilog-string-remove-spaces (match-string-no-properties 1)) ; sig
nil nil nil)) ; vec multidim mem
;;
((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
(verilog-read-sub-decls-sig
submoddecls comment port
submoddecls par-values comment port
(verilog-string-remove-spaces (match-string-no-properties 1)) ; sig
(match-string-no-properties 2) nil nil)) ; vec multidim mem
;; Fastpath was above looking-at's.
;; For something more complicated invoke a parser
((looking-at "[^)]+")
(verilog-read-sub-decls-expr
submoddecls comment port
submoddecls par-values comment port
(buffer-substring-no-properties
(point) (1- (progn (search-backward "(") ; start at (
(verilog-forward-sexp-ign-cmt 1)
(point)))))))) ; expr
;;
(forward-line 1)))))
;;(verilog-read-sub-decls-line (verilog-subdecls-new nil nil nil nil nil) "Cmt")
;;(verilog-read-sub-decls-line (verilog-subdecls-new nil nil nil nil nil) nil "Cmt")

(defun verilog-read-sub-decls-gate (submoddecls comment submod end-inst-point)
(defun verilog-read-sub-decls-gate (submoddecls par-values comment submod end-inst-point)
"For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
Inserts the list of signals found."
(save-excursion
Expand All @@ -8855,7 +8895,7 @@ Inserts the list of signals found."
(setq verilog-read-sub-decls-gate-ios (or (car iolist) "input")
iolist (cdr iolist))
(verilog-read-sub-decls-expr
submoddecls comment "primitive_port"
submoddecls par-values comment "primitive_port"
(match-string 0)))
(t
(forward-char 1)
Expand All @@ -8881,13 +8921,16 @@ Outputs comments above subcell signals, for example:
.in (in));"
(save-excursion
(let ((end-mod-point (verilog-get-end-of-defun))
st-point end-inst-point
st-point end-inst-point par-values
;; below 3 modified by verilog-read-sub-decls-line
sigs-out sigs-inout sigs-in sigs-intf sigs-intfd)
(verilog-beg-of-defun-quick)
(while (verilog-re-search-forward-quick "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
(save-excursion
(goto-char (match-beginning 0))
(setq par-values (and verilog-auto-inst-param-value
verilog-auto-inst-param-value-type
(verilog-read-inst-param-value)))
(unless (verilog-inside-comment-or-string-p)
;; Attempt to snarf a comment
(let* ((submod (verilog-read-inst-module))
Expand All @@ -8905,7 +8948,7 @@ Outputs comments above subcell signals, for example:
(point))
st-point (point))
(forward-char 1)
(verilog-read-sub-decls-gate submoddecls comment submod end-inst-point))
(verilog-read-sub-decls-gate submoddecls par-values comment submod end-inst-point))
;; Non-primitive
(t
(when (setq submodi (verilog-modi-lookup submod t))
Expand All @@ -8919,19 +8962,19 @@ Outputs comments above subcell signals, for example:
;; However I want it to be runnable even on user's manually added signals
(let ((verilog-read-sub-decls-in-interfaced t))
(while (re-search-forward "\\s *(?\\s *// Interfaced" end-inst-point t)
(verilog-read-sub-decls-line submoddecls comment))) ; Modifies sigs-ifd
(verilog-read-sub-decls-line submoddecls par-values comment))) ; Modifies sigs-ifd
(goto-char st-point)
(while (re-search-forward "\\s *(?\\s *// Interfaces" end-inst-point t)
(verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-out
(verilog-read-sub-decls-line submoddecls par-values comment)) ; Modifies sigs-out
(goto-char st-point)
(while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
(verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-out
(verilog-read-sub-decls-line submoddecls par-values comment)) ; Modifies sigs-out
(goto-char st-point)
(while (re-search-forward "\\s *(?\\s *// Inouts" end-inst-point t)
(verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-inout
(verilog-read-sub-decls-line submoddecls par-values comment)) ; Modifies sigs-inout
(goto-char st-point)
(while (re-search-forward "\\s *(?\\s *// Inputs" end-inst-point t)
(verilog-read-sub-decls-line submoddecls comment)) ; Modifies sigs-in
(verilog-read-sub-decls-line submoddecls par-values comment)) ; Modifies sigs-in
)))))))
;; Combine duplicate bits
;;(setq rr (vector sigs-out sigs-inout sigs-in))
Expand Down Expand Up @@ -9122,7 +9165,7 @@ IGNORE-NEXT is true to ignore next token, fake from inside case statement."
;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
(setq ignore-next nil rvalue semi-rvalue)
(if (not exit-keywd) (setq end-else-check t)))
((member keywd '("case" "casex" "casez"))
((member keywd '("case" "casex" "casez" "randcase"))
(skip-syntax-forward "w_")
(verilog-read-always-signals-recurse "endcase" t nil)
(setq ignore-next nil rvalue semi-rvalue)
Expand Down Expand Up @@ -13064,7 +13107,7 @@ Typing \\[verilog-auto] will make this into:
(verilog-read-signals
(save-excursion
(verilog-re-search-backward-quick
"\\(@\\|\\<\\(begin\\|if\\|case\\|always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
"\\(@\\|\\<\\(begin\\|if\\|case[xz]?\\|always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
(point))
(point)))))
(save-excursion
Expand Down

0 comments on commit 7a6f15d

Please sign in to comment.