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New procedure for image and font read from memory
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@leonow32
leonow32 committed Jun 9, 2024
1 parent d117bc8 commit a584a54
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Showing 9 changed files with 301 additions and 160 deletions.
2 changes: 1 addition & 1 deletion vga/05_text_terminal/font_0_127.mem
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Expand Up @@ -14,7 +14,7 @@ FF
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130 changes: 92 additions & 38 deletions vga/05_text_terminal/memory.v
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Expand Up @@ -11,35 +11,33 @@ module Memory(
input wire [7:0] DataFromUART_i,

// Read request from VGA controller to the memory
input wire ReadRequest_i,
input wire GetImageRequest_i,
input wire [6:0] Column_i, // Range 0..79
input wire [4:0] Row_i, // Range 0..29
input wire [3:0] Line_i, // Range 0..15
input wire [3:0] Line_i, // Range 0..15 (each char is made of 16 lines)

// Output from font memory to VGA controller
output reg [7:0] Pixels_o,
output reg [2:0] ColorForeground_o,
output reg [2:0] ColorBackground_o
);

// Variables to handle data write to image memory
reg WriteStep1;
reg WriteStep2;
reg WriteRequest;
reg [7:0] WriteBuffer;
reg [12:0] WriteAddress;

reg [7:0] ColorBuffer;
// reg [2:0] ColorForeground;
// reg [2:0] ColorBackground;

// Currently pointed character to be written
reg [6:0] CursorX; // Range 0..79
reg [4:0] CursorY; // Range 0..29

wire [31:0] WriteCharNum = CursorY * 80 + CursorX; // Range 0..2399
wire [31:0] ReadCharNum = Row_i * 80 + Column_i;

// State machine to analyze data from UART
// State machine to analyze data from UART and save it to image RAM
always @(posedge Clock, negedge Reset) begin
if(!Reset) begin
WriteStep1 <= 0;
Expand Down Expand Up @@ -135,49 +133,103 @@ module Memory(
end
end

// Read ASCII and color form image RAM

reg [12:0] ReadAddress;
reg [10:0] FontAddress;

wire [31:0] ReadCharNum = Row_i * 80 + Column_i; // Range 0..2399

reg [2:0] ReadState;
localparam WAITING_FOR_REQUEST = 0;
localparam DUMMY = 1;
localparam READ_ASCII_CODE = 2;


always @(posedge Clock, negedge Reset) begin
if(!Reset) begin
ReadState <= WAITING_FOR_REQUEST;
ReadAddress <=0;
FontAddress <= 0;
Pixels_o <= 0;
ColorForeground_o <= 0;
ColorBackground_o <= 0;
end

else case(ReadState)
0: begin
if(GetImageRequest_i) begin
ReadAddress[12:0] <= {ReadCharNum[11:0], 1'b0}; // Request ASCII code from image RAM
ReadState <= ReadState + 1'b1; // Go to next state
end
end

1: begin
ReadAddress[12:0] <= {ReadCharNum[11:0], 1'b1}; // Request color from image RAM
ReadState <= ReadState + 1'b1; // Go to next state
end

2: begin
FontAddress <= {DataFromImageRAM[6:0], Line_i[3:0]}; // Request font bitmap, DataFromImageRAM is ASCII code requested two clocls earlier
ReadState <= ReadState + 1'b1; // Go to next state
end

3: begin
// Do nothing here, just wait for FontROM to output pixel data
ReadState <= ReadState + 1'b1; // Go to next state
end

4: begin
Pixels_o <= DataFromFontROM[7:0];
ColorForeground_o <= DataFromImageRAM[6:4];
ColorBackground_o <= DataFromImageRAM[2:0];
ReadState <= 0;
end

endcase
end

// Memory of text and color
// Each EBR can store 1024x8 bit

// Text and color memory
// Image memory - text and color data





// wire [15:0] DataFromTextRAM;
wire [7:0] DataFromImageRAM;

PseudoDualPortRAM #(
.ADDRESS_WIDTH(13),
.DATA_WIDTH(8),
.MEMORY_DEPTH(4800)
) DataRAM(
) ImageRAM(
.ReadClock(Clock),
.WriteClock(Clock),
.Reset(Reset),
.ReadEnable_i(1'b1),
.WriteEnable_i(WriteRequest),
// .ReadAddress_i(ReadAddress),
.ReadAddress_i(13'd0),
.ReadAddress_i(ReadAddress),
.WriteAddress_i(WriteAddress),
.Data_i(WriteBuffer),
// .Data_o(DataFromTextRAM)
.Data_o()
.Data_o(DataFromImageRAM)
);



/*
wire [7:0] DataFromTextRAM_0;
wire [7:0] DataFromTextRAM_1;
wire [7:0] DataFromTextRAM_2;
wire [7:0] DataFromTextRAM_3;
wire [7:0] DataFromTextRAM_4;
wire [7:0] DataFromTextRAM = (TextReadAddress[11:9] == 3'd0) ? DataFromTextRAM_0 :
(TextReadAddress[11:9] == 3'd1) ? DataFromTextRAM_1 :
(TextReadAddress[11:9] == 3'd2) ? DataFromTextRAM_2 :
(TextReadAddress[11:9] == 3'd3) ? DataFromTextRAM_3 :
DataFromTextRAM_4;
wire [7:0] DataFromImageRAM_0;
wire [7:0] DataFromImageRAM_1;
wire [7:0] DataFromImageRAM_2;
wire [7:0] DataFromImageRAM_3;
wire [7:0] DataFromImageRAM_4;
wire [7:0] DataFromImageRAM = (TextReadAddress[11:9] == 3'd0) ? DataFromImageRAM_0 :
(TextReadAddress[11:9] == 3'd1) ? DataFromImageRAM_1 :
(TextReadAddress[11:9] == 3'd2) ? DataFromImageRAM_2 :
(TextReadAddress[11:9] == 3'd3) ? DataFromImageRAM_3 :
DataFromImageRAM_4;
PseudoDualPortRAM #(
.ADDRESS_WIDTH(9),
Expand All @@ -192,7 +244,7 @@ module Memory(
.ReadAddress_i(TextReadAddress[8:0]),
.WriteAddress_i(TextWriteAddress[8:0]),
.Data_i(TextDataToWrite),
.Data_o(DataFromTextRAM_0)
.Data_o(DataFromImageRAM_0)
);
PseudoDualPortRAM #(
Expand All @@ -208,7 +260,7 @@ module Memory(
.ReadAddress_i(TextReadAddress[8:0]),
.WriteAddress_i(TextWriteAddress[8:0]),
.Data_i(TextDataToWrite),
.Data_o(DataFromTextRAM_1)
.Data_o(DataFromImageRAM_1)
);
PseudoDualPortRAM #(
Expand All @@ -224,7 +276,7 @@ module Memory(
.ReadAddress_i(TextReadAddress[8:0]),
.WriteAddress_i(TextWriteAddress[8:0]),
.Data_i(TextDataToWrite),
.Data_o(DataFromTextRAM_2)
.Data_o(DataFromImageRAM_2)
);
PseudoDualPortRAM #(
Expand All @@ -240,7 +292,7 @@ module Memory(
.ReadAddress_i(TextReadAddress[8:0]),
.WriteAddress_i(TextWriteAddress[8:0]),
.Data_i(TextDataToWrite),
.Data_o(DataFromTextRAM_3)
.Data_o(DataFromImageRAM_3)
);
PseudoDualPortRAM #(
Expand All @@ -256,7 +308,7 @@ module Memory(
.ReadAddress_i(TextReadAddress[8:0]),
.WriteAddress_i(TextWriteAddress[8:0]),
.Data_i(TextDataToWrite),
.Data_o(DataFromTextRAM_4)
.Data_o(DataFromImageRAM_4)
);
*/

Expand All @@ -272,7 +324,7 @@ module Memory(
// 16 bytes per characher.
// Whole memory is 2048 bytes.

/*

wire [7:0] DataFromFontROM;

ROM #(
Expand All @@ -284,19 +336,21 @@ module Memory(
.Clock(Clock),
.Reset(Reset),
.ReadEnable_i(1'b1),
.Address_i({
DataFromTextRAM[6:0],
Line_i[3:0]
}),
.Address_i(FontAddress),
// .Address_i({
// DataFromImageRAM[6:0],
// Line_i[3:0]
// }),
.Data_o(DataFromFontROM)
);

/*
reg [1:0] DelayLine;
always @(posedge Clock, negedge Reset) begin
if(!Reset)
DelayLine <= 3'b001;
else if(ReadRequest_i)
else if(GetImageRequest_i)
DelayLine <= 3'b001;
else
DelayLine <= DelayLine << 1;
Expand All @@ -311,9 +365,9 @@ module Memory(
else if(DelayLine[1]) begin
Pixels_o <= DataFromFontROM;
// Pixels_o <= DataFromTextRAM[7:0];
// ColorForeground_o <= DataFromTextRAM[14:12];
// ColorBackground_o <= DataFromTextRAM[10:8];
// Pixels_o <= DataFromImageRAM[7:0];
// ColorForeground_o <= DataFromImageRAM[14:12];
// ColorBackground_o <= DataFromImageRAM[10:8];
ColorForeground_o <= 3'b011;
ColorBackground_o <= 3'b001;
end
Expand Down
8 changes: 4 additions & 4 deletions vga/05_text_terminal/top.v
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Expand Up @@ -26,7 +26,7 @@ module top #(
wire [3:0] Line; // Range 0..15

// Signals between memory and VGA modules
wire MemoryReadRequest;
wire GetImageRequest;
wire [7:0] Pixels;
wire [2:0] ColorForeground;
wire [2:0] ColorBackground;
Expand Down Expand Up @@ -55,7 +55,7 @@ module top #(
.AnalyzeRequest_i(DataReceivedEvent),
.DataFromUART_i(DataFromUART),

.ReadRequest_i(MemoryReadRequest),
.GetImageRequest_i(GetImageRequest),
.Column_i(Column),
.Row_i(Row),
.Line_i(Line),
Expand All @@ -70,7 +70,7 @@ module top #(
.Clock(Clock),
.Reset(Reset),

.MemoryReadRequest_o(MemoryReadRequest),
.GetImageRequest_o(GetImageRequest),
.Column_o(Column),
.Row_o(Row),
.Line_o(Line),
Expand Down Expand Up @@ -113,7 +113,7 @@ module top #(

// /* .Data_i({
// DebugTextDataToWrite,
// DebugDataFromTextRAM
// DebugDataFromImageRAM
// }),*/

// .Data_i({
Expand Down
39 changes: 39 additions & 0 deletions vga/05_text_terminal/top_01_uart_tx_rx.gtkw
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Original file line number Diff line number Diff line change
@@ -0,0 +1,39 @@
[*]
[*] GTKWave Analyzer v3.3.100 (w)1999-2019 BSI
[*] Sun Jun 09 17:26:05 2024
[*]
[dumpfile] "C:\verilog\vga\05_text_terminal\top.vcd"
[dumpfile_mtime] "Sun Jun 09 17:24:51 2024"
[dumpfile_size] 51942717
[savefile] "C:\verilog\vga\05_text_terminal\top_01_uart_tx_rx.gtkw"
[timestart] 0
[size] 1920 1009
[pos] -9 -9
*-20.663961 2010000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top_tb.
[treeopen] top_tb.DUT.
[treeopen] top_tb.DUT.Memory_inst.
[sst_width] 246
[signals_width] 248
[sst_expanded] 1
[sst_vpaned_height] 286
@200
-UART Transmitter
@28
[color] 3
top_tb.TxRequest
@22
top_tb.TxData[7:0]
@28
top_tb.TxRxCommon
@200
-UART Receiver
@820
top_tb.DUT.DataFromUART[7:0]
@22
top_tb.DUT.DataFromUART[7:0]
@28
[color] 3
top_tb.DUT.DataReceivedEvent
[pattern_trace] 1
[pattern_trace] 0
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