Nerged text and color memory into one

leonow32 · May 30, 2024 · 3aad6b5 · 3aad6b5
1 parent 7783a17
commit 3aad6b5
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diff --git a/vga/05_text_terminal/memory.v b/vga/05_text_terminal/memory.v
@@ -1,28 +1,154 @@
-// 240525
+// 240528
 
 `default_nettype none
 
-`default_nettype wire
 module Memory(
-	input  wire Clock,		// Must be 25 MHz or 25.175 MHz
-	input  wire Reset,
-
-	input Request_i,
-	input [6:0] Column,
-	input [4:0] Row,
-	input [3:0] Line,
+	input wire Clock,
+	input wire Reset,
 
-	output
+	input AnalyzeRequest_i,
+	input [7:0] DataFromUART_i,
 
+	input ReadRequest_i,
+	input [6:0] Column_i,
+	input [4:0] Row_i,
+	input [3:0] Line_i,
 
+	output [7:0] Pixels_o,
+	output [5:0] Color_o
 );
-
+
+	reg WriteRequest;
+	reg [7:0] Color;
+	reg [6:0] CursorX;									// Range 0..79
+	reg [4:0] CursorY;
+
+
+	// State machine to analyze data from UART
+
+	// Jeżeli DataFromUART_i[7] == 0 to odebrany został bajt
+	// i musi zostać zapisany do pamięci razem z 
+	// ostatnio odebranym rejestrem kolorów, po czym inkrementujemy
+	// adres pamięci o 1 (jeden adres przechwouje tekst i kolor)
+	// Jeżeli DataFromUART_i[7] == 1 to odebrany został kolor i 
+	// należy go zapisać do tymczasowego rejestru kolorów.
+
+
+
+	always @(posedge Clock, negedge Reset) begin
+		if(!Reset) begin
+			WriteRequest <= 0;
+			Color <= 6'b111_000;	// Foreground RGB, background RGB
+			CursorX <= 0;
+			CursorY <= 0;
+		end 
+
+		// If new data was received be UART module
+		// Then analyze what to do with this data
+		else if(AnalyzeRequest_i) begin
+			casex(DataFromUART_i)
+
+				// New line
+				8'h10: begin
+					if(CursorY != 29)
+						CursorY <= CursorY + 1;
+					else
+						CursorY <= 0;
+				end
+
+				// Carrige return
+				8'h13: begin
+					CursorX <= 0;
+				end
+
+				// Backspace
+				8'h08: begin
+					if(CursorX != 0)
+						CursorX <= CursorX - 1'b1;
+					else begin
+						CursorX <= 79;
+						if(CursorY != 0)
+							CursorY <= CursorY - 1'b1;
+						else
+							CursorY <= 29;
+					end
+				end
+
+				// Cursor back to home
+				8'h00,
+				8'h1B: begin
+					CursorX <= 0;
+					CursorY <= 0;
+				end
+
+				// Text
+				8'b0XXXXXXX: begin
+					WriteRequest <= 1;
+				end
+
+				// Color
+				8'b1XXXXXXX: begin
+					Color <= {
+						DataFromUART_i[6:4],
+						DataFromUART_i[2:0]
+					};
+				end
+
+			endcase
+		end
+
+		// If previously received data has to be saved
+		// Then save it to the memory and increment the cursors
+		else if(WriteRequest) begin
+			WriteRequest <= 0;
+
+			if(CursorX != 79) begin
+				CursorX <= CursorX + 1;
+			end else begin
+				CursorX <= 0;
+				if(CursorY != 29)
+					CursorY <= CursorY + 1;
+				else
+					CursorY <= 0;
+			end
+		end
+	end
+
+	// Memory of text and color
 	// Pamięć tekstu i koloru
 	// 2400 wpisów po 16 bitów
 	// EBR może pracować w układzie 512x18bit
 
+	// Text and color memory
+	wire [11:0] TextWriteAddress = CursorY * 80 + CursorX;		// Range 0..2399
+	wire [11:0] TextReadAddress;
+
+	PseudoDualPortRAM #(
+		.ADDRESS_WIDTH(12),
+		.DATA_WIDTH(16),
+		.MEMORY_DEPTH(2400)
+	) TextRAM(
+		.ReadClock(Clock),
+		.WriteClock(Clock),
+		.Reset(Reset),
+		.ReadEnable_i(1'b1),							// Czy to potrzebne
+		.WriteEnable_i(WriteRequest),
+		.ReadAddress_i(12'd0),
+		.WriteAddress_i(TextWriteAddress),
+		.Data_i({
+			1'b0, 
+			Color[5:3], 
+			1'b0, 
+			Color[2:0], 
+			DataFromUART_i[7:0]
+		}),
+		.Data_o()
+	);
+
 	// Pamięć czcionki
 	// Znaki od 0 do 127, 16 bajtów na znak
 	// 2048 bajtów na całą pamięć czcionki
 
 endmodule
+
+`default_nettype wire
diff --git a/vga/05_text_terminal/top.bat b/vga/05_text_terminal/top.bat
@@ -2,6 +2,7 @@
 iverilog -o top.o 											^
 	top.v 													^
 	top_tb.v 												^
+	memory.v												^
 	vga.v													^
 	../../edge_detector/edge_detector.v						^
 	../../ram_pseudo_dual_port/ram_pdp.v					^

diff --git a/vga/05_text_terminal/top.gtkw b/vga/05_text_terminal/top.gtkw
@@ -1,21 +1,22 @@
 [*]
 [*] GTKWave Analyzer v3.3.100 (w)1999-2019 BSI
-[*] Mon May 27 20:04:29 2024
+[*] Thu May 30 19:45:31 2024
 [*]
 [dumpfile] "C:\verilog\vga\05_text_terminal\top.vcd"
-[dumpfile_mtime] "Mon May 27 18:53:35 2024"
-[dumpfile_size] 49377387
+[dumpfile_mtime] "Thu May 30 19:45:11 2024"
+[dumpfile_size] 42775832
 [savefile] "C:\verilog\vga\05_text_terminal\top.gtkw"
-[timestart] 15252360000
-[size] 1920 1009
+[timestart] 0
+[size] 1536 793
 [pos] -1 -1
-*-18.034590 15253287722 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-28.034590 782960342 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] top_tb.
 [treeopen] top_tb.DUT.
+[treeopen] top_tb.DUT.Memory_inst.
 [sst_width] 246
 [signals_width] 297
 [sst_expanded] 1
-[sst_vpaned_height] 297
+[sst_vpaned_height] 221
 @28
 top_tb.Reset
 top_tb.Clock
@@ -31,29 +32,28 @@ top_tb.TxRxCommon
 @200
 -UART Receiver
 @28
-top_tb.DUT.DataReceived
+top_tb.DUT.DataReceivedEvent
 @820
 top_tb.DUT.DataFromUART[7:0]
 @22
 top_tb.DUT.DataFromUART[7:0]
 @200
 -Decoder
-@28
-top_tb.DUT.CharWriteRequest
 @24
-top_tb.DUT.CursorX[6:0]
-top_tb.DUT.CursorY[4:0]
+top_tb.DUT.Memory_inst.CursorX[6:0]
+top_tb.DUT.Memory_inst.CursorY[4:0]
 @200
--Character RAM
+-Text and color memory
+@23
+top_tb.TextRAM_0000[15:0]
 @22
-top_tb.CharRAM_0000[7:0]
-top_tb.CharRAM_0001[7:0]
-top_tb.CharRAM_0002[7:0]
-top_tb.CharRAM_1023[7:0]
-top_tb.CharRAM_1024[7:0]
-top_tb.CharRAM_2047[7:0]
-top_tb.CharRAM_2048[7:0]
-top_tb.CharRAM_2399[7:0]
+top_tb.TextRAM_0001[15:0]
+top_tb.TextRAM_0002[15:0]
+top_tb.TextRAM_0003[15:0]
+top_tb.TextRAM_0004[15:0]
+top_tb.TextRAM_0005[15:0]
+top_tb.TextRAM_0006[15:0]
+top_tb.TextRAM_0007[15:0]
 @200
 -VGA module
 @24
@@ -62,7 +62,7 @@ top_tb.DUT.VGA_inst.HCounter[9:0]
 top_tb.DUT.VGA_inst.Column_o[6:0]
 top_tb.DUT.VGA_inst.Row_o[4:0]
 top_tb.DUT.VGA_inst.Line_o[3:0]
-@29
+@28
 top_tb.DUT.VGA_inst.MemoryReadRequest_o
 [pattern_trace] 1
 [pattern_trace] 0
diff --git a/vga/05_text_terminal/top.v b/vga/05_text_terminal/top.v
@@ -18,7 +18,7 @@ module top #(
 );
 
 	// UART data receiver
-	wire DataReceived;
+	wire DataReceivedEvent;
 	wire [7:0] DataFromUART;
 
 	UartRx #(
@@ -28,11 +28,26 @@ module top #(
 		.Clock(Clock),
 		.Reset(Reset),
 		.Rx_i(UartRx_i),
-		.Done_o(DataReceived),
+		.Done_o(DataReceivedEvent),
 		.Data_o(DataFromUART)
 	);
 
+	// Memory controller
+	Memory Memory_inst(
+		.Clock(Clock),
+		.Reset(Reset),
+		.AnalyzeRequest_i(DataReceivedEvent),
+		.DataFromUART_i(DataFromUART),
+		.ReadRequest_i(1'b0),
+		.Column_i(7'd0),
+		.Row_i(5'd0),
+		.Line_i(4'd0),
+		.Pixels_o(),
+		.Color_o()
+	);
+
 	// Cursor pointers
+	/*
 	reg  [ 6:0] CursorX;									// Range 0..79
 	reg  [ 4:0] CursorY;									// Range 0..29
 	
@@ -48,7 +63,7 @@ module top #(
 			CharWriteRequest  <= 0;
 		end 
 		
-		else if(DataReceived) begin
+		else if(DataReceivedEvent) begin
 			casex(DataFromUART)
 				
 				// Color
@@ -104,9 +119,10 @@ module top #(
 			CharWriteRequest  <= 0;
 		end
 	end
-
+	*/
 
 	// Character memory
+	/*
 	wire [11:0] CharWriteAddress = CursorY * 80 + CursorX;		// Range 0..2399
 	wire [11:0] CharReadAddress;
 	
@@ -167,8 +183,10 @@ module top #(
 		.Data_i(DataFromUART),
 		.Data_o(CharDataFromRAM_2)
 	);
+	*/
 
 	// Font Memory
+	/*
 	wire [10:0] FontAddress;
 	
 	wire [7:0] FontDataFromROM_0;
@@ -202,7 +220,7 @@ module top #(
 		.Address_i(FontAddress[9:0]),
 		.Data_o(FontDataFromROM_1)
 	);
-
+	*/
 
 	// VGA instance
 	VGA VGA_inst(