Skip to content

Commit

Permalink
net: ethernet: xilinx: Add support for ZynqMP
Browse files Browse the repository at this point in the history 
This patch does the 64-bit changes in the driver inorder
to make it work for ZynqMP.
---> New API for axi dma buffer descriptor writes.
---> use phys_addr_offset for sw_id_offset filed to store skb address.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
  • Loading branch information
@kedareswararao
kedareswararao authored and Michal Simek committed Feb 22, 2016
1 parent 3734016 commit b5823f1
Show file tree
Hide file tree
Showing 2 changed files with 30 additions and 11 deletions.
2 changes: 1 addition & 1 deletion drivers/net/ethernet/xilinx/xilinx_axienet.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -399,7 +399,7 @@ struct axidma_bd {
u32 app2; /* TX csum seed */
u32 app3;
u32 app4;
u32 sw_id_offset;
phys_addr_t sw_id_offset; /* first unused field by h/w */
u32 ptp_tx_skb;
u32 ptp_tx_ts_tag;
phys_addr_t tx_skb;
Expand Down
39 changes: 29 additions & 10 deletions drivers/net/ethernet/xilinx/xilinx_axienet_main.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -150,6 +150,25 @@ static inline void axienet_dma_out32(struct axienet_local *lp,
out_be32((lp->dma_regs + reg), value);
}

/**
* axienet_dma_bdout - Memory mapped Axi DMA register Buffer Descriptor write.
* @lp: Pointer to axienet local structure
* @reg: Address offset from the base address of the Axi DMA core
* @value: Value to be written into the Axi DMA register
*
* This function writes the desired value into the corresponding Axi DMA
* register.
*/
static inline void axienet_dma_bdout(struct axienet_local *lp,
off_t reg, dma_addr_t value)
{
#if defined(CONFIG_PHYS_ADDR_T_64BIT)
writeq(value, (lp->dma_regs + reg));
#else
writel(value, (lp->dma_regs + reg));
#endif
}

/**
* axienet_dma_bd_release - Release buffer descriptor rings
* @ndev: Pointer to the net_device structure
Expand Down Expand Up @@ -239,7 +258,7 @@ static int axienet_dma_bd_init(struct net_device *ndev)
*/
wmb();

lp->rx_bd_v[i].sw_id_offset = (u32) skb;
lp->rx_bd_v[i].sw_id_offset = (phys_addr_t) skb;
lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
skb->data,
lp->max_frm_size,
Expand Down Expand Up @@ -276,18 +295,18 @@ static int axienet_dma_bd_init(struct net_device *ndev)
/* Populate the tail pointer and bring the Rx Axi DMA engine out of
* halted state. This will make the Rx side ready for reception.
*/
axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
axienet_dma_bdout(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
cr | XAXIDMA_CR_RUNSTOP_MASK);
axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
axienet_dma_bdout(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
(sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));

/* Write to the RS (Run-stop) bit in the Tx channel control register.
* Tx channel is now ready to run. But only after we write to the
* tail pointer register that the Tx channel will start transmitting.
*/
axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
axienet_dma_bdout(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
cr | XAXIDMA_CR_RUNSTOP_MASK);
Expand Down Expand Up @@ -889,7 +908,7 @@ static int axienet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
wmb();

/* Start the transfer */
axienet_dma_out32(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);
axienet_dma_bdout(lp, XAXIDMA_TX_TDESC_OFFSET, tail_p);
++lp->tx_bd_tail;
lp->tx_bd_tail %= TX_BD_NUM;

Expand Down Expand Up @@ -1006,7 +1025,7 @@ static int axienet_recv(struct net_device *ndev, int budget)
DMA_FROM_DEVICE);
cur_p->cntrl = lp->max_frm_size;
cur_p->status = 0;
cur_p->sw_id_offset = (u32) new_skb;
cur_p->sw_id_offset = (phys_addr_t) new_skb;

++lp->rx_bd_ci;
lp->rx_bd_ci %= RX_BD_NUM;
Expand All @@ -1021,7 +1040,7 @@ static int axienet_recv(struct net_device *ndev, int budget)
ndev->stats.rx_bytes += size;

if (tail_p)
axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);
axienet_dma_bdout(lp, XAXIDMA_RX_TDESC_OFFSET, tail_p);

return numbdfree;
}
Expand Down Expand Up @@ -1927,18 +1946,18 @@ static void axienet_dma_err_handler(unsigned long data)
/* Populate the tail pointer and bring the Rx Axi DMA engine out of
* halted state. This will make the Rx side ready for reception.
*/
axienet_dma_out32(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
axienet_dma_bdout(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
cr = axienet_dma_in32(lp, XAXIDMA_RX_CR_OFFSET);
axienet_dma_out32(lp, XAXIDMA_RX_CR_OFFSET,
cr | XAXIDMA_CR_RUNSTOP_MASK);
axienet_dma_out32(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
axienet_dma_bdout(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
(sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));

/* Write to the RS (Run-stop) bit in the Tx channel control register.
* Tx channel is now ready to run. But only after we write to the
* tail pointer register that the Tx channel will start transmitting
*/
axienet_dma_out32(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
axienet_dma_bdout(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET);
axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET,
cr | XAXIDMA_CR_RUNSTOP_MASK);
Expand Down

0 comments on commit b5823f1

Please sign in to comment.