Update verilog-mode from upstream

gmlarumbe · Sep 11, 2020 · 7ca7108 · 7ca7108
1 parent fec110f
commit 7ca7108
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diff --git a/elisp/verilog-mode/build.sh b/elisp/verilog-mode/build.sh
@@ -13,7 +13,7 @@ done
 cd ./src/ || exit
 
 make clean
-make
+make e/verilog-mode.elc
 if [[ "${run_test}" -eq 1 ]]
 then
     make -j 8 test

diff --git a/elisp/verilog-mode/src b/elisp/verilog-mode/src