diff --git a/doc/architecture.md b/doc/architecture.md index 71cc244..8ad1b3d 100644 --- a/doc/architecture.md +++ b/doc/architecture.md @@ -112,11 +112,11 @@ from the excellent Clifford Cummings. ### Clock Domain Crossing -The core provides a CDC stage for each master or slave interface if needed. The stage is +The core provides a CDC stage for each master or slave interface if needed. The stage is activated with `MSTx_CDC` or `SLVx_CDC`. Internally, the switching fabric uses a specific clock (`aclk`) to route the requests and the completions from/to the agents. The master -and slave interfaces must activate a CDC stage if they don't use the same clock than -the fabric (same frequency & phase). If an agent uses the same clock than the fabric, the +and slave interfaces must activate a CDC stage if they don't use the same clock than +the fabric (same frequency & phase). If an agent uses the same clock than the fabric, the agent must also use the same reset to ensure a clean reset sequence. @@ -127,7 +127,7 @@ sequence: 1. Drive low all the reset inputs 2. Source all the clocks of the active interface 3. Wait for several clock cycles, for each clock domain, to be sure the whole logic has been reset -4. Before releasing the resets, be sure all the domains has been completly reset (point 3). Some +4. Before releasing the resets, be sure all the domains has been completly reset (point 3). Some clock can be very slower than another domain, be sure to take it in account. 5. Release the resets 6. Start to issue request in the core @@ -162,8 +162,8 @@ BUSER and RUSER). These bus fields of the AMBA channels can be activated individually, e.g. for address channel only and configured to any width. This applies for both AXI4 and AXI4-lite configuration. -The core proposes a top level for [AXI4](../rtl/axicb_crossbar_top.sv), and a -top level for [AXI4-lite](../rtl/axicb_crossbar_lite_top.sv). Each supports up +The core proposes a top level for [AXI4](../rtl/axicb_crossbar_top.sv), and a +top level for [AXI4-lite](../rtl/axicb_crossbar_lite_top.sv). Each supports up to 4 masters and 4 slaves. If the user needs less than 4 agents, it can tied to 0 the input signals of an interface, and leave unconnected the outputs. @@ -226,8 +226,8 @@ interfaces with two parameters: - `MSTx_OSTDREQ_NUM` or `SLVx_OSTDREQ_NUM`: the maximum number of oustanding requests the core is capable to store - `MSTx_OSTDREQ_SIZE` or `SLVx_OSTDREQ_SIZE`: the number of datpahases of an - outstanding requets. Can be useful to save area if a system doesn't need to - use biggest AXI4 payload possible, i.e. if a processor only use [1,2,4,8,16] + outstanding requets. Can be useful to save area if a system doesn't need to + use biggest AXI4 payload possible, i.e. if a processor only use [1,2,4,8,16] dataphases maximum. Default should be `256` beats. When an inteface enables the CDC support to cross its clock domain, the internal @@ -270,21 +270,27 @@ All slave switches can target any master switch to drive read/write requests, while any master switch can drive back completions to any slave switch. ``` - │ │ - │ │ - ▼ ▼ -┌─────────────────────────────────────────────┐ -│ ┌──────────────┐ ┌──────────────┐ │ -│ │ slv0 switch │ │ slv1 switch │ │ -│ └──────────────┘ └──────────────┘ │ -│ │ -│ ┌──────────────┐ ┌──────────────┐ │ -│ │ mst0 switch │ │ mst1 switch │ │ -│ └──────────────┘ └──────────────┘ │ -└─────────────────────────────────────────────┘ - │ │ - │ │ - ▼ ▼ + + │ │ + │ │ + ▼ ▼ + ┌─────────────────────────────────────────────┐ + │ ┌──────────────┐ ┌──────────────┐ │ + │ │slv0 pipeline │ ..... │slvX pipeline │ │ + │ └──────────────┘ └──────────────┘ │ + │ ┌──────────────┐ ┌──────────────┐ │ + │ │ slv0 switch │ ..... │ slvX switch │ │ + │ └──────────────┘ └──────────────┘ │ + │ ┌──────────────┐ ┌──────────────┐ │ + │ │ mst0 switch │ ..... │ mstX switch │ │ + │ └──────────────┘ └──────────────┘ │ + │ ┌──────────────┐ ┌──────────────┐ │ + │ │mst0 pipeline │ ..... │mstX pipeline │ │ + │ └──────────────┘ └──────────────┘ │ + └─────────────────────────────────────────────┘ + │ │ + │ │ + ▼ ▼ ``` A pipeline stage can be activated for input and output of the switch layer to @@ -302,23 +308,23 @@ completion if needed by its internal core. ``` - From slave interface + From slave interface - AW Channel W Channel B channel AR Channel R Channel + AW Channel W Channel B channel AR Channel R Channel - │ │ ▲ │ ▲ - │ │ │ │ │ - ▼ ▼ │ ▼ │ -┌──────────────┐ ┌────┐ ┌──────────────┐ ┌──────────────┐ ┌──────────────┐ ┌──────────────┐ -│decoder+router│──▶│FIFO│──│decoder+router│ │arbiter+switch│ │decoder+router│ │arbiter+switch│ -└──────────────┘ └────┘ └──────────────┘ └──────────────┘ └──────────────┘ └──────────────┘ - │ │ │ │ ▲ ▲ │ │ ▲ ▲ - │ │ │ │ │ │ │ │ │ │ - ▼ ▼ ▼ ▼ │ │ ▼ ▼ │ │ + │ │ ▲ │ ▲ + │ │ │ │ │ + ▼ ▼ │ ▼ │ + ┌──────────────┐ ┌────┐ ┌──────────────┐ ┌──────────────┐ ┌──────────────┐ ┌──────────────┐ + │decoder+router│──▶│FIFO│──│decoder+router│ │arbiter+switch│ │decoder+router│ │arbiter+switch│ + └──────────────┘ └────┘ └──────────────┘ └──────────────┘ └──────────────┘ └──────────────┘ + │ │ │ │ ▲ ▲ │ │ ▲ ▲ + │ │ │ │ │ │ │ │ │ │ + ▼ ▼ ▼ ▼ │ │ ▼ ▼ │ │ - To master switches + To master switches ``` ### Switching Logic to Master Interfaces @@ -328,23 +334,23 @@ A fair-share round robin arbitration ensures a fair traffic share from the maste completion are routed back to the requester by decoding the ID. ``` - From slave switches + From slave switches - AW Channels W Channels B channels AR Channels R Channels + AW Channels W Channels B channels AR Channels R Channels - │ │ │ │ ▲ ▲ │ │ ▲ ▲ - │ │ │ │ │ │ │ │ │ │ - ▼ ▼ ▼ ▼ │ │ ▼ ▼ │ │ -┌──────────────┐ ┌──────────────┐ ┌──────────────┐ ┌──────────────┐ ┌──────────────┐ -│arbiter+switch│ │arbiter+switch│ │arbiter+switch│ │decoder+router│ │decoder+router│ -└──────────────┘ └──────────────┘ └──────────────┘ └──────────────┘ └──────────────┘ - │ │ ▲ │ ▲ - │ │ │ │ │ - ▼ ▼ │ ▼ │ + │ │ │ │ ▲ ▲ │ │ ▲ ▲ + │ │ │ │ │ │ │ │ │ │ + ▼ ▼ ▼ ▼ │ │ ▼ ▼ │ │ + ┌──────────────┐ ┌──────────────┐ ┌──────────────┐ ┌──────────────┐ ┌──────────────┐ + │arbiter+switch│ │arbiter+switch│ │arbiter+switch│ │decoder+router│ │decoder+router│ + └──────────────┘ └──────────────┘ └──────────────┘ └──────────────┘ └──────────────┘ + │ │ ▲ │ ▲ + │ │ │ │ │ + ▼ ▼ │ ▼ │ - To master interface + To master interface ``` diff --git a/doc/assets/intro.monopic b/doc/assets/intro.monopic index 75ed79e..d2e8fb7 100644 Binary files a/doc/assets/intro.monopic and b/doc/assets/intro.monopic differ diff --git a/rtl/axicb_slv_switch_rd.sv b/rtl/axicb_slv_switch_rd.sv index bcc0d27..507513d 100644 --- a/rtl/axicb_slv_switch_rd.sv +++ b/rtl/axicb_slv_switch_rd.sv @@ -257,18 +257,18 @@ module axicb_slv_switch_rd assign rch_req = o_rvalid; assign i_rvalid = (!rch_mr_empty && !rch_running) ? 1'b1 : - (rch_grant[0]) ? o_rvalid[0] : - (rch_grant[1]) ? o_rvalid[1] : - (rch_grant[2]) ? o_rvalid[2] : - (rch_grant[3]) ? o_rvalid[3] : - 1'b0; + (rch_grant[0]) ? o_rvalid[0] : + (rch_grant[1]) ? o_rvalid[1] : + (rch_grant[2]) ? o_rvalid[2] : + (rch_grant[3]) ? o_rvalid[3] : + 1'b0; assign i_rlast = (!rch_mr_empty && !rch_running) ? (rlen==rch_mr_len) & i_rvalid & i_rready : - (rch_grant[0]) ? o_rlast[0] : - (rch_grant[1]) ? o_rlast[1] : - (rch_grant[2]) ? o_rlast[2] : - (rch_grant[3]) ? o_rlast[3] : - 1'b0; + (rch_grant[0]) ? o_rlast[0] : + (rch_grant[1]) ? o_rlast[1] : + (rch_grant[2]) ? o_rlast[2] : + (rch_grant[3]) ? o_rlast[3] : + 1'b0; assign o_rready[0] = rch_grant[0] & i_rready & (rch_mr_empty | rch_running); assign o_rready[1] = rch_grant[1] & i_rready & (rch_mr_empty | rch_running); @@ -276,11 +276,11 @@ module axicb_slv_switch_rd assign o_rready[3] = rch_grant[3] & i_rready & (rch_mr_empty | rch_running); assign i_rch = (!rch_mr_empty && !rch_running) ? {{RCH_W-AXI_ID_W-2{1'b0}}, 2'h3, rch_mr_id} : - (rch_grant[0]) ? o_rch[0*RCH_W+:RCH_W] : - (rch_grant[1]) ? o_rch[1*RCH_W+:RCH_W] : - (rch_grant[2]) ? o_rch[2*RCH_W+:RCH_W] : - (rch_grant[3]) ? o_rch[3*RCH_W+:RCH_W] : - {RCH_W{1'b0}}; + (rch_grant[0]) ? o_rch[0*RCH_W+:RCH_W] : + (rch_grant[1]) ? o_rch[1*RCH_W+:RCH_W] : + (rch_grant[2]) ? o_rch[2*RCH_W+:RCH_W] : + (rch_grant[3]) ? o_rch[3*RCH_W+:RCH_W] : + {RCH_W{1'b0}}; endmodule diff --git a/rtl/axicb_slv_switch_wr.sv b/rtl/axicb_slv_switch_wr.sv index a053029..dd9a25d 100644 --- a/rtl/axicb_slv_switch_wr.sv +++ b/rtl/axicb_slv_switch_wr.sv @@ -143,10 +143,10 @@ module axicb_slv_switch_wr endgenerate - assign o_awvalid[0] = (slv_aw_targeted[0]) ? i_awvalid : 1'b0; - assign o_awvalid[1] = (slv_aw_targeted[1]) ? i_awvalid : 1'b0; - assign o_awvalid[2] = (slv_aw_targeted[2]) ? i_awvalid : 1'b0; - assign o_awvalid[3] = (slv_aw_targeted[3]) ? i_awvalid : 1'b0; + assign o_awvalid[0] = (slv_aw_targeted[0]) ? i_awvalid & !wch_full : 1'b0; + assign o_awvalid[1] = (slv_aw_targeted[1]) ? i_awvalid & !wch_full : 1'b0; + assign o_awvalid[2] = (slv_aw_targeted[2]) ? i_awvalid & !wch_full : 1'b0; + assign o_awvalid[3] = (slv_aw_targeted[3]) ? i_awvalid & !wch_full : 1'b0; assign i_awready = (slv_aw_targeted[0]) ? o_awready[0] & !wch_full: (slv_aw_targeted[1]) ? o_awready[1] & !wch_full: