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Hit max cycle count (10000000) .. stopping

Status: Open.

#128 In chipsalliance/Cores-VeeR-EH1;

· noobwei opened on Jan 8, 2025

[bug] Case is not fully covered

Status: Open.

#127 In chipsalliance/Cores-VeeR-EH1;

· likeamahoney opened on Nov 27, 2024

extension `zicsr' required

Status: Open.

#125 In chipsalliance/Cores-VeeR-EH1;

· ahmdotm opened on Jun 19, 2024

tcl file

Status: Open.

#124 In chipsalliance/Cores-VeeR-EH1;

· ahmdotm opened on Jun 19, 2024

Has the maintenance of this repository been stopped?

Status: Open.

#123 In chipsalliance/Cores-VeeR-EH1;

· zhangkanqi opened on Jan 9, 2024

Not generate waveform when using vcs to test Hello World.

Status: Open.

#121 In chipsalliance/Cores-VeeR-EH1;

· zhangkanqi opened on Dec 10, 2023

coremark/dhrystone testing can't get 4.9 CM/MHz with rtl simulation or in FPGA

Status: Open.

#120 In chipsalliance/Cores-VeeR-EH1;

· chithize opened on Oct 26, 2023

The new feature of verilator stops building procession

Status: Open.

#118 In chipsalliance/Cores-VeeR-EH1;

· LoveMyPillow opened on Mar 6, 2023

Blocking Loads/DMA disable

Status: Open.

#116 In chipsalliance/Cores-VeeR-EH1;

· omezrich opened on Jan 24, 2023

Coremark for new extension

Status: Open.

#114 In chipsalliance/Cores-VeeR-EH1;

· HamzaShabbir517 opened on Dec 15, 2022

facing issues when C code size goes beyond 8KB

Status: Open.

#111 In chipsalliance/Cores-VeeR-EH1;

· yash-agnisys opened on Nov 8, 2022

Question about pipeline FF enable signals

Status: Open.

#110 In chipsalliance/Cores-VeeR-EH1;

· tunefish777 opened on Jun 13, 2022