2-1 Mux.cir

A1 : in std_logic;
B1 : in std_logic;
S1 : in std_logic;
Z1 : out std_logic;

A2 : in std_logic;
B2 : in std_logic;
S2 : in std_logic;
Z2 : out std_logic;

s1,s2,s3 : signal std_logic;
s4,s5,s6 : signal std_logic;
l : signal std_logic;
m : signal std_logic;
n : signal std_logic;
p : signal std_logic;
q : signal std_logic;
r : signal std_logic;

begin arch
   AND1:  AndGate2  (A1, s2, l);
   s1:    InBranch  (S1);
   NOT1:  NotGate1  (s3, n);
   AND2:  AndGate2  (n, B1, m);
   OR1:   OrGate2   (l, m, Z1);
   
   NAND1: NandGate2 (A2, s5, p);
   s4:    InBranch  (S2);
   NOT2:  NotGate1  (s6, r);
   NAND2: NandGate2 (r, B2, q);
   NAND3: NandGate2 (p, q, Z2);
end arch;