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A hardware design framework with a timing-deterministic, Rust-embedded HDL and the compilation flow.

A Hardware Pipeline Description Language

This repository contains the source codes of various hardware blocks implemented using the indigenous Python-DSL tool developed at HPC-Lab

DHLS (Dynamic High-Level Synthesis) compiler based on MLIR

slang-based frontend for Yosys

Open Logic HDL Standard Library

Altera Advanced Synthesis Cookbook 11.0

implementation of Varvara / Uxn in FPGA

ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators (ASPLOS 2023)

This project aims to enable language model inference on FPGAs, supporting AI applications in edge devices and environments with limited resources.

A GPU acceleration flow for RTL simulation with batch stimulus

Hardware description language

A Haskell to HDL (Verilog/VHDL) Compiler

The RIFFA development repository

high abstraction synthesis

Communication framework for RTL simulation and emulation.

Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)

human-in-the-loop HDL training tool

VHDL library 4 FPGAs

An attempt to recreate the RP2040 PIO in an FPGA

A configurable and approachable tool for FPGA debugging and rapid prototyping.

A work-in-progress board-level hardware description language (HDL) providing design automation through generators and block polymorphism.

Python wrapper for verilator model

A Python to VHDL compiler

Hardware Design/Visualization/Simulation/RTLGeneration Framework

A framework for writing FPGA firmware using the Rust Programming Language