HCLTech

Design Verification Engineer

HCLTech United States

HCLTech provided pay range

This range is provided by HCLTech. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$130,000.00/yr - $150,000.00/yr

Direct message the job poster from HCLTech

Position Title: ASIC Verification Engineer

Experience Required: 4+ years


About HCLTech:

HCLTech is a global technology company, home to 221,000+ people across 60 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Engineering Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. To learn how we can supercharge progress for you, visit https://www.hcltech.com/about-us.



Job Description

We are looking for an experienced ASIC Verification Engineer with a strong background in System Verilog and UVM. The ideal candidate will have a comprehensive understanding of the complete verification lifecycle, from test planning to coverage closure. You will be responsible for SOC integration and verification, bringing your expertise in various protocols such as HBI, HBM, UCIe, PCIe, Ethernet, LPDDR5, and DFT.


Key Responsibilities

  • Develop and implement verification strategies and methodologies for complex ASIC designs.
  • Create, review, and execute test plans to ensure thorough verification coverage.
  • Develop and maintain test benches and test cases using System Verilog/UVM.
  • Perform SOC integration and verification tasks, ensuring seamless integration and functionality of SOC components.
  • Collaborate with cross-functional teams to define verification requirements and deliverables.
  • Debug and resolve design and verification issues, working closely with design and architecture teams.
  • Analyze and report verification results, driving coverage closure and sign-off.


Qualifications

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • Minimum of 4 years of experience in ASIC verification.
  • Strong proficiency in System Verilog and UVM (Universal Verification Methodology).
  • In-depth understanding of the complete verification lifecycle, from test planning to coverage closure.
  • Hands-on experience with SOC integration and SOC verification.
  • Expertise in protocols such as HBI, HBM, UCIe, PCIe, Ethernet, LPDDR5, and DFT.
  • Strong analytical and problem-solving skills.
  • Excellent communication and teamwork abilities.


Preferred Skills

  • Experience with verification tools and simulators.
  • Knowledge of scripting languages such as Python, Perl, or Tcl.
  • Familiarity with formal verification methods.

  • Seniority level

    Mid-Senior level
  • Employment type

    Full-time
  • Job function

    Engineering
  • Industries

    IT Services and IT Consulting and Semiconductor Manufacturing

Referrals increase your chances of interviewing at HCLTech by 2x

See who you know

Get notified about new Design Verification Engineer jobs in United States.

Sign in to create job alert

Similar jobs

People also viewed

Similar Searches

Explore collaborative articles

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.

Explore More