Design Verification Engineer

Title: Design Verification Engineer

Location: San Jose, CA, Austin, TX, Phoenix, AZ

Duration: 12 Months.

Pay Rate: $75 to $80/hr

Job Description:

• Testbench development - System Verilog UVM and C tests
• Integration/development of C tests/APIs and SW build flow
• Integration/development of UVM mailboxes and HW/SW communication components
• Test plan development
• Power Aware testbench development and simulations
• Seamless porting between simulation/emulation/prototyping platforms
• Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
• Coverage collection and closure
• Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
• Engage with the team to drive continuous improvement to the verification environment to find more bugs and improve coverage
• Work as a team to grow together.
• Mentor and coach junior team members

Here’s what you need:

· A minimum of three years of experience with SoC Design Verification

· Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)

Skills: CPU, Cortex/ARM Cortex, UVM, Verilog, Test Bench

Intelliswift Software is an Equal Employment Opportunity (EEO) employer and does not discriminate on the basis of age, color, national origin, citizenship status, physical or mental disability, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, genetic information, marital status, status with regard to public assistance, veteran status or any other characteristic protected by federal, state or local law.